Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.
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| Title: | Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. |
|---|---|
| Authors: | Li, Tuo1, Shafique, Muhammad2, Ambrose, Jude Angelo3, Henkel, Jorg4, Parameswaran, Sri1 |
| Source: | IEEE Transactions on Computers. Apr2017, Vol. 66 Issue 4, p647-660. 14p. |
| Subjects: | Application-specific instruction-set processors, Fault tolerance (Engineering), Computer software, Computer architecture, Embedded computer systems |
| Abstract: | Checkpoint recovery (CR) is a classic fault-tolerance technique, which enables computing systems to execute correctly even when affected by transient faults. Although a number of software and hardware based approaches for CR does exist, these approaches usually are either too large, too slow, or require extensive modifications to the software and the caching/memory schemes. In this paper, we propose a novel CR approach, which is based on re-engineering the instruction set of a target processor. We take the base instruction set and augment the native micro-operations, i.e., an architectural description language (ADL), with additional micro-operations to perform checkpointing at the granularity of basic blocks. The recovery mechanism is realized by three custom instructions, which can undo the corruptions caused by transient faults during instruction execution, including the values of general-purpose registers, data memory, and special-purpose registers (PC, status registers, etc.), which were incorrectly modified. Our checkpoint storage is sized according to the application program executed. The experimental results show that our approach degrades the system performance by just 0.76 percent when there is no fault, and introduces an area overhead of 44 percent on average and 79 percent in the worst case. During the fault injection test with the benchmark applications, the recovery took just 62 clock cycles (worst case). [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 121854119 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Li%2C+Tuo%22">Li, Tuo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Shafique%2C+Muhammad%22">Shafique, Muhammad</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Ambrose%2C+Jude+Angelo%22">Ambrose, Jude Angelo</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Henkel%2C+Jorg%22">Henkel, Jorg</searchLink><relatesTo>4</relatesTo><br /><searchLink fieldCode="AR" term="%22Parameswaran%2C+Sri%22">Parameswaran, Sri</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>. Apr2017, Vol. 66 Issue 4, p647-660. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Application-specific+instruction-set+processors%22">Application-specific instruction-set processors</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software%22">Computer software</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Checkpoint recovery (CR) is a classic fault-tolerance technique, which enables computing systems to execute correctly even when affected by transient faults. Although a number of software and hardware based approaches for CR does exist, these approaches usually are either too large, too slow, or require extensive modifications to the software and the caching/memory schemes. In this paper, we propose a novel CR approach, which is based on re-engineering the instruction set of a target processor. We take the base instruction set and augment the native micro-operations, i.e., an architectural description language (ADL), with additional micro-operations to perform checkpointing at the granularity of basic blocks. The recovery mechanism is realized by three custom instructions, which can undo the corruptions caused by transient faults during instruction execution, including the values of general-purpose registers, data memory, and special-purpose registers (PC, status registers, etc.), which were incorrectly modified. Our checkpoint storage is sized according to the application program executed. The experimental results show that our approach degrades the system performance by just 0.76 percent when there is no fault, and introduces an area overhead of 44 percent on average and 79 percent in the worst case. During the fault injection test with the benchmark applications, the recovery took just 62 clock cycles (worst case). [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TC.2016.2606378 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 647 Subjects: – SubjectFull: Application-specific instruction-set processors Type: general – SubjectFull: Fault tolerance (Engineering) Type: general – SubjectFull: Computer software Type: general – SubjectFull: Computer architecture Type: general – SubjectFull: Embedded computer systems Type: general Titles: – TitleFull: Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Li, Tuo – PersonEntity: Name: NameFull: Shafique, Muhammad – PersonEntity: Name: NameFull: Ambrose, Jude Angelo – PersonEntity: Name: NameFull: Henkel, Jorg – PersonEntity: Name: NameFull: Parameswaran, Sri IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 04 Text: Apr2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 00189340 Numbering: – Type: volume Value: 66 – Type: issue Value: 4 Titles: – TitleFull: IEEE Transactions on Computers Type: main |
| ResultId | 1 |
