Energy-efficient NoC with multi-granularity power optimization.
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| Title: | Energy-efficient NoC with multi-granularity power optimization. |
|---|---|
| Authors: | Wu, Ji1 wu_ji2012@163.com, Dong, Dezun1 dong@nudt.edu.cn, Liao, Xiangke1, Wang, Li1 |
| Source: | Journal of Supercomputing. Apr2017, Vol. 73 Issue 4, p1654-1671. 18p. |
| Subjects: | Networks on a chip, Energy consumption of computers, Computer network architectures, Algorithms, Systems on a chip |
| Abstract: | As the core count grows rapidly, NoC (Network-on-Chip) consumes an increasing fraction of the modern processors/SoCs (System-on-Chips) power. It is thus very important to design energy-efficient NoC architecture. Multi-NoC (Multiple Network-on-Chip) has demonstrated its advantages in power gating for reducing leakage power, which constitutes a significant fraction of NoC power. In this paper, we propose Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a congestion-aware traffic allocation policy, Chameleon is able to achieve both high performance and low power at varying network utilization. Our experimental results on both synthetic and real workloads show that Chameleon delivers an average of 2.61 % higher performance than Catnap, the best in the literature. More importantly, Chameleon consumes an average of 27.75 % less power than Catnap. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 121962957 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Energy-efficient NoC with multi-granularity power optimization. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Wu%2C+Ji%22">Wu, Ji</searchLink><relatesTo>1</relatesTo><i> wu_ji2012@163.com</i><br /><searchLink fieldCode="AR" term="%22Dong%2C+Dezun%22">Dong, Dezun</searchLink><relatesTo>1</relatesTo><i> dong@nudt.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Liao%2C+Xiangke%22">Liao, Xiangke</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Wang%2C+Li%22">Wang, Li</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Apr2017, Vol. 73 Issue 4, p1654-1671. 18p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Networks+on+a+chip%22">Networks on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption+of+computers%22">Energy consumption of computers</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+network+architectures%22">Computer network architectures</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip%22">Systems on a chip</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: As the core count grows rapidly, NoC (Network-on-Chip) consumes an increasing fraction of the modern processors/SoCs (System-on-Chips) power. It is thus very important to design energy-efficient NoC architecture. Multi-NoC (Multiple Network-on-Chip) has demonstrated its advantages in power gating for reducing leakage power, which constitutes a significant fraction of NoC power. In this paper, we propose Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a congestion-aware traffic allocation policy, Chameleon is able to achieve both high performance and low power at varying network utilization. Our experimental results on both synthetic and real workloads show that Chameleon delivers an average of 2.61 % higher performance than Catnap, the best in the literature. More importantly, Chameleon consumes an average of 27.75 % less power than Catnap. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11227-016-1859-8 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 18 StartPage: 1654 Subjects: – SubjectFull: Networks on a chip Type: general – SubjectFull: Energy consumption of computers Type: general – SubjectFull: Computer network architectures Type: general – SubjectFull: Algorithms Type: general – SubjectFull: Systems on a chip Type: general Titles: – TitleFull: Energy-efficient NoC with multi-granularity power optimization. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Wu, Ji – PersonEntity: Name: NameFull: Dong, Dezun – PersonEntity: Name: NameFull: Liao, Xiangke – PersonEntity: Name: NameFull: Wang, Li IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 04 Text: Apr2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 09208542 Numbering: – Type: volume Value: 73 – Type: issue Value: 4 Titles: – TitleFull: Journal of Supercomputing Type: main |
| ResultId | 1 |
