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NONUNIFORM CACHE ARCHITECTURES FOR WIRE-DELAY DOMINATED ON-CHIP CACHES.

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Bibliographic Details
Title: NONUNIFORM CACHE ARCHITECTURES FOR WIRE-DELAY DOMINATED ON-CHIP CACHES.
Authors: Kim, Changkyu1, Burger, Doug1, Keckler, Stephen W.1
Source: IEEE Micro. Nov/Dec2003, Vol. 23 Issue 6, p99-107. 9p.
Subjects: Cache memory, Systems design, Computer architecture, Integrated circuits, Microprocessors, Computer networks, Data transmission systems
Abstract: The article presents nonuniform cache access (NUCA) designs as a solution for on-chip wire delay problem for future large integrated caches. In this design, a switched network allows data to migrate to different cache regions according to access frequency. The frequently accessed data migrates to areas closer to the processor. The author proposes several designs that treat the cache as a network of banks and facilitate nonuniform access to different physical regions. NUCA architectures offer low latency access, increased scalability and greater performance stability than conventional uniform access cache architectures.
Database: Engineering Source
Description
Abstract:The article presents nonuniform cache access (NUCA) designs as a solution for on-chip wire delay problem for future large integrated caches. In this design, a switched network allows data to migrate to different cache regions according to access frequency. The frequently accessed data migrates to areas closer to the processor. The author proposes several designs that treat the cache as a network of banks and facilitate nonuniform access to different physical regions. NUCA architectures offer low latency access, increased scalability and greater performance stability than conventional uniform access cache architectures.
ISSN:02721732
DOI:10.1109/MM.2003.1261393