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NONUNIFORM CACHE ARCHITECTURES FOR WIRE-DELAY DOMINATED ON-CHIP CACHES.

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Title: NONUNIFORM CACHE ARCHITECTURES FOR WIRE-DELAY DOMINATED ON-CHIP CACHES.
Authors: Kim, Changkyu1, Burger, Doug1, Keckler, Stephen W.1
Source: IEEE Micro. Nov/Dec2003, Vol. 23 Issue 6, p99-107. 9p.
Subjects: Cache memory, Systems design, Computer architecture, Integrated circuits, Microprocessors, Computer networks, Data transmission systems
Abstract: The article presents nonuniform cache access (NUCA) designs as a solution for on-chip wire delay problem for future large integrated caches. In this design, a switched network allows data to migrate to different cache regions according to access frequency. The frequently accessed data migrates to areas closer to the processor. The author proposes several designs that treat the cache as a network of banks and facilitate nonuniform access to different physical regions. NUCA architectures offer low latency access, increased scalability and greater performance stability than conventional uniform access cache architectures.
Database: Engineering Source
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  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 12247096
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: NONUNIFORM CACHE ARCHITECTURES FOR WIRE-DELAY DOMINATED ON-CHIP CACHES.
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  Data: <searchLink fieldCode="AR" term="%22Kim%2C+Changkyu%22">Kim, Changkyu</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Burger%2C+Doug%22">Burger, Doug</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Keckler%2C+Stephen+W%2E%22">Keckler, Stephen W.</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Micro%22">IEEE Micro</searchLink>. Nov/Dec2003, Vol. 23 Issue 6, p99-107. 9p.
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  Data: <searchLink fieldCode="DE" term="%22Cache+memory%22">Cache memory</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+design%22">Systems design</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+networks%22">Computer networks</searchLink><br /><searchLink fieldCode="DE" term="%22Data+transmission+systems%22">Data transmission systems</searchLink>
– Name: Abstract
  Label: Abstract
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  Data: The article presents nonuniform cache access (NUCA) designs as a solution for on-chip wire delay problem for future large integrated caches. In this design, a switched network allows data to migrate to different cache regions according to access frequency. The frequently accessed data migrates to areas closer to the processor. The author proposes several designs that treat the cache as a network of banks and facilitate nonuniform access to different physical regions. NUCA architectures offer low latency access, increased scalability and greater performance stability than conventional uniform access cache architectures.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=12247096
RecordInfo BibRecord:
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        Value: 10.1109/MM.2003.1261393
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      – Code: eng
        Text: English
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        PageCount: 9
        StartPage: 99
    Subjects:
      – SubjectFull: Cache memory
        Type: general
      – SubjectFull: Systems design
        Type: general
      – SubjectFull: Computer architecture
        Type: general
      – SubjectFull: Integrated circuits
        Type: general
      – SubjectFull: Microprocessors
        Type: general
      – SubjectFull: Computer networks
        Type: general
      – SubjectFull: Data transmission systems
        Type: general
    Titles:
      – TitleFull: NONUNIFORM CACHE ARCHITECTURES FOR WIRE-DELAY DOMINATED ON-CHIP CACHES.
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            NameFull: Kim, Changkyu
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            NameFull: Burger, Doug
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            NameFull: Keckler, Stephen W.
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            – D: 01
              M: 11
              Text: Nov/Dec2003
              Type: published
              Y: 2003
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              Value: 23
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              Value: 6
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            – TitleFull: IEEE Micro
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