Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.

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Title: Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
Authors: RAJAEI, Ramin1 r_rajaei@sbu.ac.ir, ASGARI, Bahar2, TABANDEH, Mahmoud3, FAZELI, Mahdi2
Source: Turkish Journal of Electrical Engineering & Computer Sciences. 2017, Vol. 25 Issue 2, p1035-1047. 13p.
Subjects: Static random access memory chips, Complementary metal oxide semiconductors, Radiation, Soft errors, Single event effects
Abstract: In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins. [ABSTRACT FROM AUTHOR]
Copyright of Turkish Journal of Electrical Engineering & Computer Sciences is the property of Scientific and Technical Research Council of Turkey and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
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  Data: <searchLink fieldCode="AR" term="%22RAJAEI%2C+Ramin%22">RAJAEI, Ramin</searchLink><relatesTo>1</relatesTo><i> r_rajaei@sbu.ac.ir</i><br /><searchLink fieldCode="AR" term="%22ASGARI%2C+Bahar%22">ASGARI, Bahar</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22TABANDEH%2C+Mahmoud%22">TABANDEH, Mahmoud</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22FAZELI%2C+Mahdi%22">FAZELI, Mahdi</searchLink><relatesTo>2</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22Turkish+Journal+of+Electrical+Engineering+%26+Computer+Sciences%22">Turkish Journal of Electrical Engineering & Computer Sciences</searchLink>. 2017, Vol. 25 Issue 2, p1035-1047. 13p.
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  Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Radiation%22">Radiation</searchLink><br /><searchLink fieldCode="DE" term="%22Soft+errors%22">Soft errors</searchLink><br /><searchLink fieldCode="DE" term="%22Single+event+effects%22">Single event effects</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Turkish Journal of Electrical Engineering & Computer Sciences is the property of Scientific and Technical Research Council of Turkey and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.3906/elk-1502-124
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      – Code: eng
        Text: English
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        PageCount: 13
        StartPage: 1035
    Subjects:
      – SubjectFull: Static random access memory chips
        Type: general
      – SubjectFull: Complementary metal oxide semiconductors
        Type: general
      – SubjectFull: Radiation
        Type: general
      – SubjectFull: Soft errors
        Type: general
      – SubjectFull: Single event effects
        Type: general
    Titles:
      – TitleFull: Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
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            NameFull: RAJAEI, Ramin
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            NameFull: ASGARI, Bahar
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            NameFull: TABANDEH, Mahmoud
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            NameFull: FAZELI, Mahdi
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            – D: 01
              M: 03
              Text: 2017
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              Y: 2017
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            – TitleFull: Turkish Journal of Electrical Engineering & Computer Sciences
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