Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project.
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| Title: | Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. |
|---|---|
| Authors: | Jordans, Roel1 r.jordans@tue.nl, Jóźwiak, Lech1, Corporaal, Henk1, Corvino, Rosilde2 |
| Source: | Microprocessors & Microsystems. Jun2017, Vol. 51, p114-133. 20p. |
| Subjects: | Application-specific instruction-set processors, Microprocessors, Multicore processors, Problem solving, Mathematical combinations |
| Abstract: | The design of high-performance application-specific multi-core processor systems still is a time consuming task which involves many manual steps and decisions that need to be performed by experienced design engineers. The ASAM project sought to change this by proposing an automatic architecture synthesis and mapping flow aimed at the design of such application specific instruction-set processor (ASIP) systems. The ASAM flow separated the design problem into two cooperating exploration levels, known as the macro-level and micro-level exploration. This paper presents an overview of the micro-level exploration level, which is concerned with the analysis and design of individual processors within the overall multi-core design starting at the initial exploration stages but continuing up to the selection of the final design of the individual processors within the system. The designed processors use a combination of very-long instruction-word (VLIW), single-instruction multiple-data (SIMD), and complex custom DSP-like operations in order to provide an area- and energy-efficient and high-performance execution of the program parts assigned to the processor node. In this paper we present an overview of how the micro-level design space exploration interacts with the macro-level, how early performance estimates are used within the ASAM flow to determine the tasks executed by each processor node, and how an initial processor design is then proposed and refined into a highly specialized VLIW ASIP. The micro-level architecture exploration is then demonstrated with a walk-through description of the process on an example program kernel to further clarify the exploration and architecture specialization process. The main findings of the experimental research are that the presented method enables an automatic instruction-set architecture synthesis for VLIW ASIPs within a reasonable exploration time. Using the presented approach, we were able to automatically determine an initial architecture prototype that was able to meet the temporal performance requirements of the target application. Subsequently, refinement of this architecture considerably reduced both the design area (by 4x) and the active energy consumption (by 2x). [ABSTRACT FROM AUTHOR] |
| Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 123443257 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Jordans%2C+Roel%22">Jordans, Roel</searchLink><relatesTo>1</relatesTo><i> r.jordans@tue.nl</i><br /><searchLink fieldCode="AR" term="%22Jóźwiak%2C+Lech%22">Jóźwiak, Lech</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Corporaal%2C+Henk%22">Corporaal, Henk</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Corvino%2C+Rosilde%22">Corvino, Rosilde</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Jun2017, Vol. 51, p114-133. 20p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Application-specific+instruction-set+processors%22">Application-specific instruction-set processors</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Multicore+processors%22">Multicore processors</searchLink><br /><searchLink fieldCode="DE" term="%22Problem+solving%22">Problem solving</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+combinations%22">Mathematical combinations</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The design of high-performance application-specific multi-core processor systems still is a time consuming task which involves many manual steps and decisions that need to be performed by experienced design engineers. The ASAM project sought to change this by proposing an automatic architecture synthesis and mapping flow aimed at the design of such application specific instruction-set processor (ASIP) systems. The ASAM flow separated the design problem into two cooperating exploration levels, known as the macro-level and micro-level exploration. This paper presents an overview of the micro-level exploration level, which is concerned with the analysis and design of individual processors within the overall multi-core design starting at the initial exploration stages but continuing up to the selection of the final design of the individual processors within the system. The designed processors use a combination of very-long instruction-word (VLIW), single-instruction multiple-data (SIMD), and complex custom DSP-like operations in order to provide an area- and energy-efficient and high-performance execution of the program parts assigned to the processor node. In this paper we present an overview of how the micro-level design space exploration interacts with the macro-level, how early performance estimates are used within the ASAM flow to determine the tasks executed by each processor node, and how an initial processor design is then proposed and refined into a highly specialized VLIW ASIP. The micro-level architecture exploration is then demonstrated with a walk-through description of the process on an example program kernel to further clarify the exploration and architecture specialization process. The main findings of the experimental research are that the presented method enables an automatic instruction-set architecture synthesis for VLIW ASIPs within a reasonable exploration time. Using the presented approach, we were able to automatically determine an initial architecture prototype that was able to meet the temporal performance requirements of the target application. Subsequently, refinement of this architecture considerably reduced both the design area (by 4x) and the active energy consumption (by 2x). [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.micpro.2017.04.011 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 20 StartPage: 114 Subjects: – SubjectFull: Application-specific instruction-set processors Type: general – SubjectFull: Microprocessors Type: general – SubjectFull: Multicore processors Type: general – SubjectFull: Problem solving Type: general – SubjectFull: Mathematical combinations Type: general Titles: – TitleFull: Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Jordans, Roel – PersonEntity: Name: NameFull: Jóźwiak, Lech – PersonEntity: Name: NameFull: Corporaal, Henk – PersonEntity: Name: NameFull: Corvino, Rosilde IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 01419331 Numbering: – Type: volume Value: 51 Titles: – TitleFull: Microprocessors & Microsystems Type: main |
| ResultId | 1 |
