Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures.
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| Title: | Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures. |
|---|---|
| Authors: | Papadogiannaki, Eva1, Koromilas, Lazaros1, Vasiliadis, Giorgos2, Ioannidis, Sotiris1 |
| Source: | IEEE/ACM Transactions on Networking. Jun2017, Vol. 25 Issue 3, p1593-1606. 14p. |
| Subjects: | Computer software packaging, Motherboards, Graphics processing units |
| Abstract: | Heterogeneous and asymmetric computing systems are composed by a set of different processing units, each with its own unique performance and energy characteristics. Still, the majority of current network packet processing frameworks targets only a single device (the CPU or some accelerator), leaving the rest processing resources unused and idle. In this paper, we propose an adaptive scheduling approach that supports the heterogeneous and asymmetric hardware, tailored for network packet processing applications. Our scheduler is able to respond quickly to dynamic performance fluctuations that occur at real time, such as traffic bursts, application overloads, and system changes. The experimental results show that our system is able to match the peak throughput of a diverse set of packet processing applications, while consuming up to $3.5\times$ less energy. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE/ACM Transactions on Networking is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 123684934 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Papadogiannaki%2C+Eva%22">Papadogiannaki, Eva</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Koromilas%2C+Lazaros%22">Koromilas, Lazaros</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Vasiliadis%2C+Giorgos%22">Vasiliadis, Giorgos</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Ioannidis%2C+Sotiris%22">Ioannidis, Sotiris</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE%2FACM+Transactions+on+Networking%22">IEEE/ACM Transactions on Networking</searchLink>. Jun2017, Vol. 25 Issue 3, p1593-1606. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+software+packaging%22">Computer software packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Motherboards%22">Motherboards</searchLink><br /><searchLink fieldCode="DE" term="%22Graphics+processing+units%22">Graphics processing units</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Heterogeneous and asymmetric computing systems are composed by a set of different processing units, each with its own unique performance and energy characteristics. Still, the majority of current network packet processing frameworks targets only a single device (the CPU or some accelerator), leaving the rest processing resources unused and idle. In this paper, we propose an adaptive scheduling approach that supports the heterogeneous and asymmetric hardware, tailored for network packet processing applications. Our scheduler is able to respond quickly to dynamic performance fluctuations that occur at real time, such as traffic bursts, application overloads, and system changes. The experimental results show that our system is able to match the peak throughput of a diverse set of packet processing applications, while consuming up to $3.5\times$ less energy. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE/ACM Transactions on Networking is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TNET.2016.2642338 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 1593 Subjects: – SubjectFull: Computer software packaging Type: general – SubjectFull: Motherboards Type: general – SubjectFull: Graphics processing units Type: general Titles: – TitleFull: Efficient Software Packet Processing on Heterogeneous and Asymmetric Hardware Architectures. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Papadogiannaki, Eva – PersonEntity: Name: NameFull: Koromilas, Lazaros – PersonEntity: Name: NameFull: Vasiliadis, Giorgos – PersonEntity: Name: NameFull: Ioannidis, Sotiris IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 10636692 Numbering: – Type: volume Value: 25 – Type: issue Value: 3 Titles: – TitleFull: IEEE/ACM Transactions on Networking Type: main |
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