Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect.
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| Title: | Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect. |
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| Authors: | Marsan-Loyer, C.1 catherine.marsan-loyer@c2mi.ca, Danovitch, D.1, Boyer, N.2 |
| Source: | Journal of Microelectronic & Electronic Packaging. 2017 1st Quarter, Vol. 14 Issue 1, p32-38. 7p. |
| Subjects: | Chip scale packaging, Fine pitch technology, Electronic packaging, Tape-automated bonding, Microelectronics, Magnetic flux |
| Abstract: | The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new finepitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, whereas excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This article presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die (8 x 11 x 0.780 mm) with 11,343 ultrafine pitch (62 µm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behavior and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e., cleaning and underfill) as well as product reliability. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Microelectronic & Electronic Packaging is the property of International Microelectronics & Packaging Society and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Items | – Name: Title Label: Title Group: Ti Data: Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Marsan-Loyer%2C+C%2E%22">Marsan-Loyer, C.</searchLink><relatesTo>1</relatesTo><i> catherine.marsan-loyer@c2mi.ca</i><br /><searchLink fieldCode="AR" term="%22Danovitch%2C+D%2E%22">Danovitch, D.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Boyer%2C+N%2E%22">Boyer, N.</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Microelectronic+%26+Electronic+Packaging%22">Journal of Microelectronic & Electronic Packaging</searchLink>. 2017 1st Quarter, Vol. 14 Issue 1, p32-38. 7p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Fine+pitch+technology%22">Fine pitch technology</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+packaging%22">Electronic packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Tape-automated+bonding%22">Tape-automated bonding</searchLink><br /><searchLink fieldCode="DE" term="%22Microelectronics%22">Microelectronics</searchLink><br /><searchLink fieldCode="DE" term="%22Magnetic+flux%22">Magnetic flux</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new finepitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, whereas excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This article presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die (8 x 11 x 0.780 mm) with 11,343 ultrafine pitch (62 µm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behavior and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e., cleaning and underfill) as well as product reliability. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Microelectronic & Electronic Packaging is the property of International Microelectronics & Packaging Society and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.4071/imaps.348081 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 7 StartPage: 32 Subjects: – SubjectFull: Chip scale packaging Type: general – SubjectFull: Fine pitch technology Type: general – SubjectFull: Electronic packaging Type: general – SubjectFull: Tape-automated bonding Type: general – SubjectFull: Microelectronics Type: general – SubjectFull: Magnetic flux Type: general Titles: – TitleFull: Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Marsan-Loyer, C. – PersonEntity: Name: NameFull: Danovitch, D. – PersonEntity: Name: NameFull: Boyer, N. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: 2017 1st Quarter Type: published Y: 2017 Identifiers: – Type: issn-print Value: 15514897 Numbering: – Type: volume Value: 14 – Type: issue Value: 1 Titles: – TitleFull: Journal of Microelectronic & Electronic Packaging Type: main |
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