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Josephson-CMOS Hybrid Memory With Nanocryotrons.

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Title: Josephson-CMOS Hybrid Memory With Nanocryotrons.
Authors: Tanaka, Masamitsu1, Suzuki, Masato1, Konno, Gen2, Ito, Yuki1, Fujimaki, Akira1, Yoshikawa, Nobuyuki2
Source: IEEE Transactions on Applied Superconductivity. Jun2017 Part 1, Vol. 27 Issue 4, Part 1, p1-4. 4p.
Subjects: CMOS memory circuits, Cryotrons, Dynamic random access memory, Quantum logic
Abstract: We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy-efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36–2.77 mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-$\mu$m Nb/AlO $_x$/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-$\mu$ m CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of $\sim$0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Applied Superconductivity is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Josephson-CMOS Hybrid Memory With Nanocryotrons.
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  Data: <searchLink fieldCode="AR" term="%22Tanaka%2C+Masamitsu%22">Tanaka, Masamitsu</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Suzuki%2C+Masato%22">Suzuki, Masato</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Konno%2C+Gen%22">Konno, Gen</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Ito%2C+Yuki%22">Ito, Yuki</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Fujimaki%2C+Akira%22">Fujimaki, Akira</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yoshikawa%2C+Nobuyuki%22">Yoshikawa, Nobuyuki</searchLink><relatesTo>2</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Applied+Superconductivity%22">IEEE Transactions on Applied Superconductivity</searchLink>. Jun2017 Part 1, Vol. 27 Issue 4, Part 1, p1-4. 4p.
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  Data: <searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Cryotrons%22">Cryotrons</searchLink><br /><searchLink fieldCode="DE" term="%22Dynamic+random+access+memory%22">Dynamic random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Quantum+logic%22">Quantum logic</searchLink>
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  Label: Abstract
  Group: Ab
  Data: We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy-efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36–2.77 mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-$\mu$m Nb/AlO $_x$/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-$\mu$ m CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of $\sim$0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons. [ABSTRACT FROM PUBLISHER]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Applied Superconductivity is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TASC.2016.2646929
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        Text: English
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        Type: general
      – SubjectFull: Cryotrons
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      – SubjectFull: Dynamic random access memory
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      – SubjectFull: Quantum logic
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      – TitleFull: Josephson-CMOS Hybrid Memory With Nanocryotrons.
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              Text: Jun2017 Part 1
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              Y: 2017
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