On the Implementation of Computation-in-Memory Parallel Adder.
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| Title: | On the Implementation of Computation-in-Memory Parallel Adder. |
|---|---|
| Authors: | Du Nguyen, Hoang Anh1, Xie, Lei1, Taouil, Mottaqiallah1, Nane, Razvan1, Hamdioui, Said1, Bertels, Koen1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Aug2017, Vol. 25 Issue 8, p2206-2219. 14p. |
| Subjects: | CMOS memory circuits, Logic circuits, Computer integrated manufacturing systems, Implication (Logic), Adders (Digital electronics) |
| Abstract: | Today’s computer architectures suffer from many challenges, such as the near end of CMOS downscaling, the memory/communication bottleneck, the power wall, and the programming complexity. As a consequence, these architectures become inefficient in solving big data problems or general data intensive applications. Computation-in-memory (CIM) is a novel architecture that tries to solve/alleviate the impact of these challenges using the same device (i.e., the memristor) to implement the processor and memory in the same physical crossbar. In order to analyze its feasibility in depth, this paper proposes two memristor implementations of a data intensive arithmetic application (i.e., parallel addition). To the best of our knowledge, this is the first paper that considers the cost of the entire architecture including both crossbar and its CMOS controller. The results show that CIM architecture in general and the CIM parallel adder in particular have a high scalability. CIM parallel adder achieves at least two orders of magnitude improvement in energy and area in comparison with a multicore-based parallel adder. Moreover, due to a wide variety of memristor design methods (such as Boolean logic), tradeoffs can be made between the area, delay, and energy consumption. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 124331378 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: On the Implementation of Computation-in-Memory Parallel Adder. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Du+Nguyen%2C+Hoang+Anh%22">Du Nguyen, Hoang Anh</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Xie%2C+Lei%22">Xie, Lei</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Taouil%2C+Mottaqiallah%22">Taouil, Mottaqiallah</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Nane%2C+Razvan%22">Nane, Razvan</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Hamdioui%2C+Said%22">Hamdioui, Said</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Bertels%2C+Koen%22">Bertels, Koen</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Aug2017, Vol. 25 Issue 8, p2206-2219. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+integrated+manufacturing+systems%22">Computer integrated manufacturing systems</searchLink><br /><searchLink fieldCode="DE" term="%22Implication+%28Logic%29%22">Implication (Logic)</searchLink><br /><searchLink fieldCode="DE" term="%22Adders+%28Digital+electronics%29%22">Adders (Digital electronics)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Today’s computer architectures suffer from many challenges, such as the near end of CMOS downscaling, the memory/communication bottleneck, the power wall, and the programming complexity. As a consequence, these architectures become inefficient in solving big data problems or general data intensive applications. Computation-in-memory (CIM) is a novel architecture that tries to solve/alleviate the impact of these challenges using the same device (i.e., the memristor) to implement the processor and memory in the same physical crossbar. In order to analyze its feasibility in depth, this paper proposes two memristor implementations of a data intensive arithmetic application (i.e., parallel addition). To the best of our knowledge, this is the first paper that considers the cost of the entire architecture including both crossbar and its CMOS controller. The results show that CIM architecture in general and the CIM parallel adder in particular have a high scalability. CIM parallel adder achieves at least two orders of magnitude improvement in energy and area in comparison with a multicore-based parallel adder. Moreover, due to a wide variety of memristor design methods (such as Boolean logic), tradeoffs can be made between the area, delay, and energy consumption. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2017.2690571 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 2206 Subjects: – SubjectFull: CMOS memory circuits Type: general – SubjectFull: Logic circuits Type: general – SubjectFull: Computer integrated manufacturing systems Type: general – SubjectFull: Implication (Logic) Type: general – SubjectFull: Adders (Digital electronics) Type: general Titles: – TitleFull: On the Implementation of Computation-in-Memory Parallel Adder. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Du Nguyen, Hoang Anh – PersonEntity: Name: NameFull: Xie, Lei – PersonEntity: Name: NameFull: Taouil, Mottaqiallah – PersonEntity: Name: NameFull: Nane, Razvan – PersonEntity: Name: NameFull: Hamdioui, Said – PersonEntity: Name: NameFull: Bertels, Koen IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 25 – Type: issue Value: 8 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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