Energy-Aware Modeling of Scaled Heterogeneous Systems.
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| Title: | Energy-Aware Modeling of Scaled Heterogeneous Systems. |
|---|---|
| Authors: | Marowka, Ami1 amimar2@yahoo.com |
| Source: | International Journal of Parallel Programming. Oct2017, Vol. 45 Issue 5, p1026-1045. 20p. |
| Subjects: | Energy consumption management, Microprocessor energy consumption, Microprocessor design & construction, Chip scale packaging, Moore's law |
| Abstract: | Many-core processors are accelerating the performance of contemporary high-performance systems. Managing power consumption within these systems demands low-power architectures to increase power savings. One of the promising solutions offered today by microprocessor architects is asymmetric microprocessors that integrate different core architectures on a single die. This paper presents analytical models based on scaled power metrics to analyze the impact of various architectural design choices on scaled performance and power savings. The power consumption implications of different processing schemes and various chip configurations were also analyzed. Analysis shows that by choosing the optimal chip configuration, energy efficiency and energy savings can be increased considerably. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Parallel Programming is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 124504592 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Energy-Aware Modeling of Scaled Heterogeneous Systems. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Marowka%2C+Ami%22">Marowka, Ami</searchLink><relatesTo>1</relatesTo><i> amimar2@yahoo.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Parallel+Programming%22">International Journal of Parallel Programming</searchLink>. Oct2017, Vol. 45 Issue 5, p1026-1045. 20p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Energy+consumption+management%22">Energy consumption management</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessor+energy+consumption%22">Microprocessor energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessor+design+%26+construction%22">Microprocessor design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Moore's+law%22">Moore's law</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Many-core processors are accelerating the performance of contemporary high-performance systems. Managing power consumption within these systems demands low-power architectures to increase power savings. One of the promising solutions offered today by microprocessor architects is asymmetric microprocessors that integrate different core architectures on a single die. This paper presents analytical models based on scaled power metrics to analyze the impact of various architectural design choices on scaled performance and power savings. The power consumption implications of different processing schemes and various chip configurations were also analyzed. Analysis shows that by choosing the optimal chip configuration, energy efficiency and energy savings can be increased considerably. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of International Journal of Parallel Programming is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s10766-016-0453-2 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 20 StartPage: 1026 Subjects: – SubjectFull: Energy consumption management Type: general – SubjectFull: Microprocessor energy consumption Type: general – SubjectFull: Microprocessor design & construction Type: general – SubjectFull: Chip scale packaging Type: general – SubjectFull: Moore's law Type: general Titles: – TitleFull: Energy-Aware Modeling of Scaled Heterogeneous Systems. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Marowka, Ami IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 08857458 Numbering: – Type: volume Value: 45 – Type: issue Value: 5 Titles: – TitleFull: International Journal of Parallel Programming Type: main |
| ResultId | 1 |
