Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell.
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| Title: | Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell. |
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| Authors: | Singh, Shalini1 shalini.sportive@gmail.com, Akashe, Shyam1 shyam.akashe@itmuniversity.ac.in |
| Source: | Wireless Personal Communications. Sep2017, Vol. 96 Issue 1, p1099-1109. 11p. |
| Subjects: | Static random access memory chips, Energy consumption, Antenna arrays, Data warehousing, Stray currents |
| Abstract: | Rapid increase in technology is showing a great perception in assessing the complexity of design that can be integrated on a single chip dramatically. Minimum feature sizes, low power consumption, minimum cost and high performance have become the key characteristics of any electronic component. All these factors have plunged the designers into the sub micron space which brings the leakage parameters into forefront. Many electronic components especially digital designs are designed for the storage of data, highlighting the use of memory. So this paper is dedicated to the storage of data by designing 1 KB memory using SRAM. The cell used in implementing the array structure is 7T SRAM with the minimum leakage current 20.16 pA and average delay of 21 ns. This has been done in the form of an array which is a two dimensional structure of basic unit cell SRAM. The array formed in this paper is a squared array of 32 × 32. The other supporting devices in executing this array are address decoder, precharge circuit, write driver circuit and sense amplifiers. The verification of working of 1 KB SRAM array has been done in cadence virtuoso tool in 45 nm technology. [ABSTRACT FROM AUTHOR] |
| Copyright of Wireless Personal Communications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 124751285 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Singh%2C+Shalini%22">Singh, Shalini</searchLink><relatesTo>1</relatesTo><i> shalini.sportive@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Akashe%2C+Shyam%22">Akashe, Shyam</searchLink><relatesTo>1</relatesTo><i> shyam.akashe@itmuniversity.ac.in</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Wireless+Personal+Communications%22">Wireless Personal Communications</searchLink>. Sep2017, Vol. 96 Issue 1, p1099-1109. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Antenna+arrays%22">Antenna arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Data+warehousing%22">Data warehousing</searchLink><br /><searchLink fieldCode="DE" term="%22Stray+currents%22">Stray currents</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Rapid increase in technology is showing a great perception in assessing the complexity of design that can be integrated on a single chip dramatically. Minimum feature sizes, low power consumption, minimum cost and high performance have become the key characteristics of any electronic component. All these factors have plunged the designers into the sub micron space which brings the leakage parameters into forefront. Many electronic components especially digital designs are designed for the storage of data, highlighting the use of memory. So this paper is dedicated to the storage of data by designing 1 KB memory using SRAM. The cell used in implementing the array structure is 7T SRAM with the minimum leakage current 20.16 pA and average delay of 21 ns. This has been done in the form of an array which is a two dimensional structure of basic unit cell SRAM. The array formed in this paper is a squared array of 32 × 32. The other supporting devices in executing this array are address decoder, precharge circuit, write driver circuit and sense amplifiers. The verification of working of 1 KB SRAM array has been done in cadence virtuoso tool in 45 nm technology. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Wireless Personal Communications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11277-017-4226-z Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 1099 Subjects: – SubjectFull: Static random access memory chips Type: general – SubjectFull: Energy consumption Type: general – SubjectFull: Antenna arrays Type: general – SubjectFull: Data warehousing Type: general – SubjectFull: Stray currents Type: general Titles: – TitleFull: Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Singh, Shalini – PersonEntity: Name: NameFull: Akashe, Shyam IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 09296212 Numbering: – Type: volume Value: 96 – Type: issue Value: 1 Titles: – TitleFull: Wireless Personal Communications Type: main |
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