Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications.
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| Title: | Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications. |
|---|---|
| Authors: | He, Miao1, Contreras, Gustavo K.1, Tran, Dat2, Winemberg, LeRoy2, Tehranipoor, Mark1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Sep2017, Vol. 25 Issue 9, p2602-2615. 14p. |
| Subjects: | Integrated circuits, Logic circuits, Semiconductors |
| Abstract: | Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Furthermore, depending on where test points are inserted, they can create a significant area overhead unnecessarily. Therefore, we propose a novel timing-aware framework to evaluate test points’ impact on a design, rank them based on their efficiency, and obtain an optimal configuration of the most efficient test points accurately and rapidly. Specifically, the proposed framework considers not only individual test coverage improvement but also area penalty, path timing, and region in which each test point is inserted. Within this framework, we have two metrics, namely, efficient test point insertion (ETPI) and test point removal estimation (TPRE). The ETPI metric is developed to remove the most inefficient test points inserted in the circuit by commercial tools, thereby minimizing area penalty with very limited test coverage loss. The TPRE metric is introduced to estimate area overhead and test coverage for designs with different percentages (number) of test points removed without the actual insertion of test points and without the need for lengthy circuit simulation, thereby quickly selecting the most effective test point removal scheme and saving significant amount of processing time especially for large circuits. Experimental results, collected by applying the metrics to NXP Semiconductors circuits and academic benchmark circuits, indicate that ETPI can reduce area overhead by up to 95% with test coverage loss as low as 0.57%. In addition, results by applying the TPRE metric indicate that the difference between estimation and actual simulation/synthesis results for area overhead is less than 0.20% for most cases, and the difference between them for test coverage is less than 1% for most cases. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 124835250 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22He%2C+Miao%22">He, Miao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Contreras%2C+Gustavo+K%2E%22">Contreras, Gustavo K.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Tran%2C+Dat%22">Tran, Dat</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Winemberg%2C+LeRoy%22">Winemberg, LeRoy</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Tehranipoor%2C+Mark%22">Tehranipoor, Mark</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Sep2017, Vol. 25 Issue 9, p2602-2615. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductors%22">Semiconductors</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Furthermore, depending on where test points are inserted, they can create a significant area overhead unnecessarily. Therefore, we propose a novel timing-aware framework to evaluate test points’ impact on a design, rank them based on their efficiency, and obtain an optimal configuration of the most efficient test points accurately and rapidly. Specifically, the proposed framework considers not only individual test coverage improvement but also area penalty, path timing, and region in which each test point is inserted. Within this framework, we have two metrics, namely, efficient test point insertion (ETPI) and test point removal estimation (TPRE). The ETPI metric is developed to remove the most inefficient test points inserted in the circuit by commercial tools, thereby minimizing area penalty with very limited test coverage loss. The TPRE metric is introduced to estimate area overhead and test coverage for designs with different percentages (number) of test points removed without the actual insertion of test points and without the need for lengthy circuit simulation, thereby quickly selecting the most effective test point removal scheme and saving significant amount of processing time especially for large circuits. Experimental results, collected by applying the metrics to NXP Semiconductors circuits and academic benchmark circuits, indicate that ETPI can reduce area overhead by up to 95% with test coverage loss as low as 0.57%. In addition, results by applying the TPRE metric indicate that the difference between estimation and actual simulation/synthesis results for area overhead is less than 0.20% for most cases, and the difference between them for test coverage is less than 1% for most cases. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2017.2704104 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 2602 Subjects: – SubjectFull: Integrated circuits Type: general – SubjectFull: Logic circuits Type: general – SubjectFull: Semiconductors Type: general Titles: – TitleFull: Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: He, Miao – PersonEntity: Name: NameFull: Contreras, Gustavo K. – PersonEntity: Name: NameFull: Tran, Dat – PersonEntity: Name: NameFull: Winemberg, LeRoy – PersonEntity: Name: NameFull: Tehranipoor, Mark IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 25 – Type: issue Value: 9 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
