FPGA-Based Parallel Implementation of Morphological Operators for 2D Gray-Level Images.
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| Title: | FPGA-Based Parallel Implementation of Morphological Operators for 2D Gray-Level Images. |
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| Authors: | Mukherjee, Debasish1 debasish0004@cse.ism.ac.in, Mukhopadhyay, Susanta1 msushanta2001@gmail.com, Biswas, G.1 gpbiswas@gmail.com |
| Source: | Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2017, Vol. 42 Issue 8, p3191-3206. 16p. |
| Subjects: | Systolic array circuits, Parallel algorithms |
| Abstract: | In this study a parallel algorithm and its implementation on hardware platform for 2D gray-level morphological dilation/erosion using rectangular structuring element are presented. A pipelined architecture for morphological opening/closing and open-close filter is designed exploiting inter-operator parallelism among dilation/erosion operator. The proposed parallel algorithm processes pixel onstream resulting in low memory utilization. In addition, it reduces computational time with respect to image dimension. The architecture provides real-time performance for processing large-sized structuring elements on high-resolution images. Additionally, it outperforms the processing capabilities of existing delay-line-based architecture, systolic array architecture and parallel implementation in terms of frame rate. It has been observed that the proposed method achieves a maximum speedup by a factor of two and four to compute opening/closing and open-close filter compared to the equivalent non-pipelined implementation. Experimental results show that the architecture for open-close filter is able to achieve about 591 frames per second on $$566\times 566$$ images using $$9\times 9$$ rectangular structuring elements. [ABSTRACT FROM AUTHOR] |
| Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 124864683 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: FPGA-Based Parallel Implementation of Morphological Operators for 2D Gray-Level Images. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Mukherjee%2C+Debasish%22">Mukherjee, Debasish</searchLink><relatesTo>1</relatesTo><i> debasish0004@cse.ism.ac.in</i><br /><searchLink fieldCode="AR" term="%22Mukhopadhyay%2C+Susanta%22">Mukhopadhyay, Susanta</searchLink><relatesTo>1</relatesTo><i> msushanta2001@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Biswas%2C+G%2E%22">Biswas, G.</searchLink><relatesTo>1</relatesTo><i> gpbiswas@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Arabian+Journal+for+Science+%26+Engineering+%28Springer+Science+%26+Business+Media+B%2EV%2E+%29%22">Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. )</searchLink>. Aug2017, Vol. 42 Issue 8, p3191-3206. 16p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+algorithms%22">Parallel algorithms</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In this study a parallel algorithm and its implementation on hardware platform for 2D gray-level morphological dilation/erosion using rectangular structuring element are presented. A pipelined architecture for morphological opening/closing and open-close filter is designed exploiting inter-operator parallelism among dilation/erosion operator. The proposed parallel algorithm processes pixel onstream resulting in low memory utilization. In addition, it reduces computational time with respect to image dimension. The architecture provides real-time performance for processing large-sized structuring elements on high-resolution images. Additionally, it outperforms the processing capabilities of existing delay-line-based architecture, systolic array architecture and parallel implementation in terms of frame rate. It has been observed that the proposed method achieves a maximum speedup by a factor of two and four to compute opening/closing and open-close filter compared to the equivalent non-pipelined implementation. Experimental results show that the architecture for open-close filter is able to achieve about 591 frames per second on $$566\times 566$$ images using $$9\times 9$$ rectangular structuring elements. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s13369-017-2429-y Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 16 StartPage: 3191 Subjects: – SubjectFull: Systolic array circuits Type: general – SubjectFull: Parallel algorithms Type: general Titles: – TitleFull: FPGA-Based Parallel Implementation of Morphological Operators for 2D Gray-Level Images. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Mukherjee, Debasish – PersonEntity: Name: NameFull: Mukhopadhyay, Susanta – PersonEntity: Name: NameFull: Biswas, G. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 2193567X Numbering: – Type: volume Value: 42 – Type: issue Value: 8 Titles: – TitleFull: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) Type: main |
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