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Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio.

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Title: Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio.
Authors: Xiao, Zhiyi, Yao, Mingjun1, Yu, Daquan1 Daquan.yu@htkjks.com, Zhou, Minghao2, Dai, Fengwei2, Fan, Jun1, Xiang, Min1, Zhang, Wei3
Source: Microsystem Technologies. Oct2017, Vol. 23 Issue 10, p4879-4889. 11p.
Subjects: Chip scale packaging, Electroplating, Reliability in engineering, Wafer level packaging, CMOS integrated circuits, Image sensors, Aspect ratio (Images)
Abstract: 3D wafer-level chip scale packaging (3D WLCSP) using via last through silicon via (TSV) technology is an ideal technology to meet small-form-factor, high I/O density, high-speed, short time to market and lower cost product requirements. In this study, process development and reliability evaluation of 3D WLCSP for CMOS Image Sensor (CIS) using vertical TSVs with 3:1 aspect ratio were presented. Key processes including wafer bonding, wafer backside grinding, silicon etch, bottom oxide etch, via cleaning, barrier/seed layer deposition, electroplating, redistribution layer (RDL) and ball grid array (BGA) formation were developed. Reliability of the developed WLCSP was characterized by various tests. The failed devices after reliability tests were analyzed using microstructure observation and finite element simulation for stress distribution of TSV structure. The results indicate that WLCSP with vertical via last scheme can provide a reliable, low-cost solution for the next-generation CIS requiring high density routing. [ABSTRACT FROM AUTHOR]
Copyright of Microsystem Technologies is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 125148085
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PubType: Academic Journal
PubTypeId: academicJournal
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Xiao%2C+Zhiyi%22">Xiao, Zhiyi</searchLink><br /><searchLink fieldCode="AR" term="%22Yao%2C+Mingjun%22">Yao, Mingjun</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yu%2C+Daquan%22">Yu, Daquan</searchLink><relatesTo>1</relatesTo><i> Daquan.yu@htkjks.com</i><br /><searchLink fieldCode="AR" term="%22Zhou%2C+Minghao%22">Zhou, Minghao</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Dai%2C+Fengwei%22">Dai, Fengwei</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Fan%2C+Jun%22">Fan, Jun</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Xiang%2C+Min%22">Xiang, Min</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Wei%22">Zhang, Wei</searchLink><relatesTo>3</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Microsystem+Technologies%22">Microsystem Technologies</searchLink>. Oct2017, Vol. 23 Issue 10, p4879-4889. 11p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Electroplating%22">Electroplating</searchLink><br /><searchLink fieldCode="DE" term="%22Reliability+in+engineering%22">Reliability in engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Wafer+level+packaging%22">Wafer level packaging</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Image+sensors%22">Image sensors</searchLink><br /><searchLink fieldCode="DE" term="%22Aspect+ratio+%28Images%29%22">Aspect ratio (Images)</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: 3D wafer-level chip scale packaging (3D WLCSP) using via last through silicon via (TSV) technology is an ideal technology to meet small-form-factor, high I/O density, high-speed, short time to market and lower cost product requirements. In this study, process development and reliability evaluation of 3D WLCSP for CMOS Image Sensor (CIS) using vertical TSVs with 3:1 aspect ratio were presented. Key processes including wafer bonding, wafer backside grinding, silicon etch, bottom oxide etch, via cleaning, barrier/seed layer deposition, electroplating, redistribution layer (RDL) and ball grid array (BGA) formation were developed. Reliability of the developed WLCSP was characterized by various tests. The failed devices after reliability tests were analyzed using microstructure observation and finite element simulation for stress distribution of TSV structure. The results indicate that WLCSP with vertical via last scheme can provide a reliable, low-cost solution for the next-generation CIS requiring high density routing. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Microsystem Technologies is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/s00542-016-3267-7
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 11
        StartPage: 4879
    Subjects:
      – SubjectFull: Chip scale packaging
        Type: general
      – SubjectFull: Electroplating
        Type: general
      – SubjectFull: Reliability in engineering
        Type: general
      – SubjectFull: Wafer level packaging
        Type: general
      – SubjectFull: CMOS integrated circuits
        Type: general
      – SubjectFull: Image sensors
        Type: general
      – SubjectFull: Aspect ratio (Images)
        Type: general
    Titles:
      – TitleFull: Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Xiao, Zhiyi
      – PersonEntity:
          Name:
            NameFull: Yao, Mingjun
      – PersonEntity:
          Name:
            NameFull: Yu, Daquan
      – PersonEntity:
          Name:
            NameFull: Zhou, Minghao
      – PersonEntity:
          Name:
            NameFull: Dai, Fengwei
      – PersonEntity:
          Name:
            NameFull: Fan, Jun
      – PersonEntity:
          Name:
            NameFull: Xiang, Min
      – PersonEntity:
          Name:
            NameFull: Zhang, Wei
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 10
              Text: Oct2017
              Type: published
              Y: 2017
          Identifiers:
            – Type: issn-print
              Value: 09467076
          Numbering:
            – Type: volume
              Value: 23
            – Type: issue
              Value: 10
          Titles:
            – TitleFull: Microsystem Technologies
              Type: main
ResultId 1