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PGMA: An algorithmic approach for multi-objective hardware software partitioning.

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Title: PGMA: An algorithmic approach for multi-objective hardware software partitioning.
Authors: Govil, Naman1 naman.govil@research.iiit.ac.in, Shrestha, Rahul2 rahul_shrestha@iitmandi.ac.in, Roy Chowdhury, Shubhajit2 src@iitmandi.ac.in
Source: Microprocessors & Microsystems. Oct2017, Vol. 54, p83-96. 14p.
Subjects: Parallel algorithms, Embedded computer system design & construction, Computational complexity, Systems design, JPEG (Image coding standard)
Abstract: Designing embedded systems efficiently has always been of significant interest. This has been tremendously scaled-up for contemporary and high-end applications with their increasing complexity and the need to satisfy multiple conflicting constraints. This paper presents a high-speed Hardware Software Partitioning technique for the design of such systems. The partitioning problem has been modeled as a multi-dimensional optimization problem with the aim of minimizing the area utilization, power dissipation, time of execution and system memory requirement of the implementation. A two-phased algorithm (Phased Greedy Metaheuristic Algorithm or PGMA) has been proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Subsequently, a detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed. The execution time is as low as 18 ms for partitioning an algorithm consisting of 1000 blocks. Thereafter, the proposed algorithm is applied to a real-life embedded system, the Joint Photographic Expert-Group (JPEG) Encoder, to demonstrate its effectiveness. For a power constraint of 600 mW, an area utilization of 58.28% has been achieved, which is the maximum amongst all the reported works till date, to the best of our knowledge. This allowed for a decreased offloading of tasks to software, resulting in a memory usage of only 14 KB and execution time of 20 ms. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:Designing embedded systems efficiently has always been of significant interest. This has been tremendously scaled-up for contemporary and high-end applications with their increasing complexity and the need to satisfy multiple conflicting constraints. This paper presents a high-speed Hardware Software Partitioning technique for the design of such systems. The partitioning problem has been modeled as a multi-dimensional optimization problem with the aim of minimizing the area utilization, power dissipation, time of execution and system memory requirement of the implementation. A two-phased algorithm (Phased Greedy Metaheuristic Algorithm or PGMA) has been proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Subsequently, a detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed. The execution time is as low as 18 ms for partitioning an algorithm consisting of 1000 blocks. Thereafter, the proposed algorithm is applied to a real-life embedded system, the Joint Photographic Expert-Group (JPEG) Encoder, to demonstrate its effectiveness. For a power constraint of 600 mW, an area utilization of 58.28% has been achieved, which is the maximum amongst all the reported works till date, to the best of our knowledge. This allowed for a decreased offloading of tasks to software, resulting in a memory usage of only 14 KB and execution time of 20 ms. [ABSTRACT FROM AUTHOR]
ISSN:01419331
DOI:10.1016/j.micpro.2017.09.002