A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures.
Saved in:
| Title: | A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures. |
|---|---|
| Authors: | Aljafar, Muayad J.1, Perkowski, Marek A.1, Acken, John M.1, Tan, Robin1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2018, Vol. 26 Issue 1, p23-36. 14p. |
| Subjects: | CMOS logic circuits, Programmable circuits, Data structures |
| Abstract: | This paper describes a CMOS-memristive programmable logic device connected to CMOS XOR gates (mPLD-XOR) for realizing multioutput functions well suited for two-level {NAND, AND, NOR, OR}-XOR-based design. This structure is a generalized form of AND–XOR logic where any combination of NAND, AND, NOR, and OR, and literals can replace the and level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels of functions are implemented with novel programmable diode gates, which rely on the diode-like behavior of self-rectifying memristors, and the output levels of functions are realized with CMOS modulo-two counters. As an example, the circuit implementation of a 3-bit adder and a 3-bit multiplier are presented. The size and performance of the implemented circuits are estimated and compared with those of the equivalent circuits realized with stateful logic gates. Adding a feedback circuit to the mPLD-XOR allows the implementation of a multilevel XOR logic network with any combination of sums, products, XORs, and literals at the input of any XOR gate. The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 127046588 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Aljafar%2C+Muayad+J%2E%22">Aljafar, Muayad J.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Perkowski%2C+Marek+A%2E%22">Perkowski, Marek A.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Acken%2C+John+M%2E%22">Acken, John M.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Tan%2C+Robin%22">Tan, Robin</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Jan2018, Vol. 26 Issue 1, p23-36. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22CMOS+logic+circuits%22">CMOS logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+circuits%22">Programmable circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Data+structures%22">Data structures</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper describes a CMOS-memristive programmable logic device connected to CMOS XOR gates (mPLD-XOR) for realizing multioutput functions well suited for two-level {NAND, AND, NOR, OR}-XOR-based design. This structure is a generalized form of AND–XOR logic where any combination of NAND, AND, NOR, and OR, and literals can replace the and level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels of functions are implemented with novel programmable diode gates, which rely on the diode-like behavior of self-rectifying memristors, and the output levels of functions are realized with CMOS modulo-two counters. As an example, the circuit implementation of a 3-bit adder and a 3-bit multiplier are presented. The size and performance of the implemented circuits are estimated and compared with those of the equivalent circuits realized with stateful logic gates. Adding a feedback circuit to the mPLD-XOR allows the implementation of a multilevel XOR logic network with any combination of sums, products, XORs, and literals at the input of any XOR gate. The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=127046588 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2017.2750074 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 23 Subjects: – SubjectFull: CMOS logic circuits Type: general – SubjectFull: Programmable circuits Type: general – SubjectFull: Data structures Type: general Titles: – TitleFull: A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Aljafar, Muayad J. – PersonEntity: Name: NameFull: Perkowski, Marek A. – PersonEntity: Name: NameFull: Acken, John M. – PersonEntity: Name: NameFull: Tan, Robin IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 26 – Type: issue Value: 1 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
