Bibliographic Details
| Title: |
A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation. |
| Authors: |
Liu, Lianxi1, Mu, Junchao2, Zhu, Zhangming1 |
| Source: |
IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Jan2018, Vol. 65 Issue 1, p95-106. 12p. |
| Subjects: |
CMOS memory circuits, Threshold voltage, Capacitors |
| Abstract: |
This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER] |
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| Database: |
Engineering Source |
