A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation.
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| Title: | A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation. |
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| Authors: | Liu, Lianxi1, Mu, Junchao2, Zhu, Zhangming1 |
| Source: | IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Jan2018, Vol. 65 Issue 1, p95-106. 12p. |
| Subjects: | CMOS memory circuits, Threshold voltage, Capacitors |
| Abstract: | This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 127252285 AccessLevel: 6 PubType: Periodical PubTypeId: serialPeriodical PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Liu%2C+Lianxi%22">Liu, Lianxi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Mu%2C+Junchao%22">Mu, Junchao</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhu%2C+Zhangming%22">Zhu, Zhangming</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+I%3A+Regular+Papers%22">IEEE Transactions on Circuits & Systems. Part I: Regular Papers</searchLink>. Jan2018, Vol. 65 Issue 1, p95-106. 12p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Threshold+voltage%22">Threshold voltage</searchLink><br /><searchLink fieldCode="DE" term="%22Capacitors%22">Capacitors</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCSI.2017.2711923 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 12 StartPage: 95 Subjects: – SubjectFull: CMOS memory circuits Type: general – SubjectFull: Threshold voltage Type: general – SubjectFull: Capacitors Type: general Titles: – TitleFull: A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Liu, Lianxi – PersonEntity: Name: NameFull: Mu, Junchao – PersonEntity: Name: NameFull: Zhu, Zhangming IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 15498328 Numbering: – Type: volume Value: 65 – Type: issue Value: 1 Titles: – TitleFull: IEEE Transactions on Circuits & Systems. Part I: Regular Papers Type: main |
| ResultId | 1 |
