APA (7th ed.) Citation

Fang, S., & Wu, K. (2017). Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(2), 581. https://doi.org/10.1109/TVLSI.2016.2600681

Chicago Style (17th ed.) Citation

Fang, Shao-Yun, and Kuo-Hao Wu. "Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 2 (2017): 581. https://doi.org/10.1109/TVLSI.2016.2600681.

MLA (9th ed.) Citation

Fang, Shao-Yun, and Kuo-Hao Wu. "Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, 2017, p. 581, https://doi.org/10.1109/TVLSI.2016.2600681.