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Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing.

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Title: Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing.
Authors: Shao-Yun Fang1, Kuo-Hao Wu1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Feb2017, Vol. 25 Issue 2, p581-593. 13p.
Subjects: Lithography techniques, Routing algorithms, Structural optimization
Abstract: Because of the delay of the next-generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20-nm technology nodes. For advanced sub-10-nm nodes, self-aligned quadruple patterning (SAQP) or even self-aligned octuple patterning will be required. Due to considerable design complexity and unmanageable process variation, 1-D grid-based layout structure will be adopted, which can be achieved with sophisticated self-aligned multiple patterning (SAMP) process with the use of a cut mask. However, cut masks for arbitrary layouts are hardly manufacturable, because cut mask rules are limited by conventional 193-nm lithography. To the best of our knowledge, most of the existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. We first identify cut mask-aware routing rules to guide our router. Then, cut mask-aware wire planning, detailed routing, and postlayout modification techniques are proposed in the routing flow. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing.
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  Data: <searchLink fieldCode="DE" term="%22Lithography+techniques%22">Lithography techniques</searchLink><br /><searchLink fieldCode="DE" term="%22Routing+algorithms%22">Routing algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Structural+optimization%22">Structural optimization</searchLink>
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  Data: Because of the delay of the next-generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20-nm technology nodes. For advanced sub-10-nm nodes, self-aligned quadruple patterning (SAQP) or even self-aligned octuple patterning will be required. Due to considerable design complexity and unmanageable process variation, 1-D grid-based layout structure will be adopted, which can be achieved with sophisticated self-aligned multiple patterning (SAMP) process with the use of a cut mask. However, cut masks for arbitrary layouts are hardly manufacturable, because cut mask rules are limited by conventional 193-nm lithography. To the best of our knowledge, most of the existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. We first identify cut mask-aware routing rules to guide our router. Then, cut mask-aware wire planning, detailed routing, and postlayout modification techniques are proposed in the routing flow. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TVLSI.2016.2600681
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        Text: English
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        PageCount: 13
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        Type: general
      – SubjectFull: Routing algorithms
        Type: general
      – SubjectFull: Structural optimization
        Type: general
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      – TitleFull: Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing.
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            NameFull: Shao-Yun Fang
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              Text: Feb2017
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