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Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.

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Title: Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.
Authors: Ding, Yixiao1, Chu, Chris1, Mak, Wai-Kei2
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Mar2018, Vol. 37 Issue 3, p657-668. 12p.
Subjects: Lithography, Patterning therapy, Routing (Computer network management), Dielectrics, Heuristic algorithms
Abstract: In 10nm technology node, self-aligned double patterning (SADP) and triple patterning lithography (TPL) allow us to achieve minimum wiring pitch of around 45nm. While metal layers can be printed by SADP, via layer manufacturing requires TPL to maintain design rules. SADP-aware detailed routing is proposed to ensure decomposability of metal layer patterns. However, its routing solution does not automatically guarantee TPL decomposable via layers. Vias have an inherently low reliability and via failure causes a great yield loss. Double via insertion (DVI) is an effective means to increase yield by reducing via failures. With the restriction of SADP design rules and consideration of TPL decomposability for via layers, DVI becomes a more challenging problem. In this paper, we consider DVI and via layer TPL manufacturability simultaneously in SADP-aware detailed routing. Both spacer-is-metal and spacer-is-dielectric types of SADP are considered. Furthermore, we tackle the TPL-aware DVI in postrouting stage. Both ILP and high-performance heuristic solutions are proposed. The experimental results demonstrate our router can obtain 100% routability and TPL decomposable via layers with reduced dead via count. Meanwhile, compared with the ILP approach to solve TPL-aware DVI problem, the heuristic approach can achieve similar solution quality and significant speedup. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
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  Data: Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.
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  Data: <searchLink fieldCode="AR" term="%22Ding%2C+Yixiao%22">Ding, Yixiao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chu%2C+Chris%22">Chu, Chris</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Mak%2C+Wai-Kei%22">Mak, Wai-Kei</searchLink><relatesTo>2</relatesTo>
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  Data: <searchLink fieldCode="DE" term="%22Lithography%22">Lithography</searchLink><br /><searchLink fieldCode="DE" term="%22Patterning+therapy%22">Patterning therapy</searchLink><br /><searchLink fieldCode="DE" term="%22Routing+%28Computer+network+management%29%22">Routing (Computer network management)</searchLink><br /><searchLink fieldCode="DE" term="%22Dielectrics%22">Dielectrics</searchLink><br /><searchLink fieldCode="DE" term="%22Heuristic+algorithms%22">Heuristic algorithms</searchLink>
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  Label: Abstract
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  Data: In 10nm technology node, self-aligned double patterning (SADP) and triple patterning lithography (TPL) allow us to achieve minimum wiring pitch of around 45nm. While metal layers can be printed by SADP, via layer manufacturing requires TPL to maintain design rules. SADP-aware detailed routing is proposed to ensure decomposability of metal layer patterns. However, its routing solution does not automatically guarantee TPL decomposable via layers. Vias have an inherently low reliability and via failure causes a great yield loss. Double via insertion (DVI) is an effective means to increase yield by reducing via failures. With the restriction of SADP design rules and consideration of TPL decomposability for via layers, DVI becomes a more challenging problem. In this paper, we consider DVI and via layer TPL manufacturability simultaneously in SADP-aware detailed routing. Both spacer-is-metal and spacer-is-dielectric types of SADP are considered. Furthermore, we tackle the TPL-aware DVI in postrouting stage. Both ILP and high-performance heuristic solutions are proposed. The experimental results demonstrate our router can obtain 100% routability and TPL decomposable via layers with reduced dead via count. Meanwhile, compared with the ILP approach to solve TPL-aware DVI problem, the heuristic approach can achieve similar solution quality and significant speedup. [ABSTRACT FROM PUBLISHER]
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  Label:
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  Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TCAD.2017.2712660
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      – Code: eng
        Text: English
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        PageCount: 12
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      – SubjectFull: Lithography
        Type: general
      – SubjectFull: Patterning therapy
        Type: general
      – SubjectFull: Routing (Computer network management)
        Type: general
      – SubjectFull: Dielectrics
        Type: general
      – SubjectFull: Heuristic algorithms
        Type: general
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      – TitleFull: Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.
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            NameFull: Ding, Yixiao
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            NameFull: Chu, Chris
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            NameFull: Mak, Wai-Kei
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              M: 03
              Text: Mar2018
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              Y: 2018
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