Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.
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| Title: | Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design. |
|---|---|
| Authors: | Prakash, Alok1, Clarke, Christopher T.2, Lam, Siew-Kei1, Srikanthan, Thambipillai1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Mar2018, Vol. 26 Issue 3, p445-456. 12p. |
| Subjects: | Systems on a chip, Integrated memory circuits, Embedded computer systems |
| Abstract: | Programmable Systems-on-Chips (SoCs) are expected to incorporate a larger number of application-specific hardware accelerators with tightly integrated memories in order to meet stringent performance-power requirements of embedded systems. As data sharing between the accelerator memories and the processor is inevitable, it is of paramount importance that the selection of application segments for hardware acceleration must be undertaken such that the communication overhead of data transfers do not impede the advantages of the accelerators. In this paper, we propose a novel memory-aware selection algorithm that is based on an iterative approach to rapidly recommend a set of hardware accelerators that will provide high performance gain under varying area constraint. In order to significantly reduce the algorithm runtime while still guaranteeing near-optimal solutions, we propose a heuristic to estimate the penalties incurred when the processor accesses the accelerator memories. In each iteration of the proposed algorithm, a two-pass method is employed where a set of good hardware accelerator candidates is selected using a greedy approach in the first pass, and a “sliding window” approach is used in the second pass to refine the solution. The two-pass method is iteratively performed on a bounded set of candidate hardware accelerators to limit the search space and to avoid local maxima. In order to validate the benefits of the proposed selection algorithm, an exhaustive search algorithm is also developed. Experimental results using the popular CHStone benchmark suite show that the performance achieved by the accelerators recommended by the proposed algorithm closely matches the performance of the exhaustive algorithm, with close to 99% accuracy, while being orders of magnitude faster. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 128188857 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Prakash%2C+Alok%22">Prakash, Alok</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Clarke%2C+Christopher+T%2E%22">Clarke, Christopher T.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Lam%2C+Siew-Kei%22">Lam, Siew-Kei</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Srikanthan%2C+Thambipillai%22">Srikanthan, Thambipillai</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Mar2018, Vol. 26 Issue 3, p445-456. 12p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Systems+on+a+chip%22">Systems on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Programmable Systems-on-Chips (SoCs) are expected to incorporate a larger number of application-specific hardware accelerators with tightly integrated memories in order to meet stringent performance-power requirements of embedded systems. As data sharing between the accelerator memories and the processor is inevitable, it is of paramount importance that the selection of application segments for hardware acceleration must be undertaken such that the communication overhead of data transfers do not impede the advantages of the accelerators. In this paper, we propose a novel memory-aware selection algorithm that is based on an iterative approach to rapidly recommend a set of hardware accelerators that will provide high performance gain under varying area constraint. In order to significantly reduce the algorithm runtime while still guaranteeing near-optimal solutions, we propose a heuristic to estimate the penalties incurred when the processor accesses the accelerator memories. In each iteration of the proposed algorithm, a two-pass method is employed where a set of good hardware accelerator candidates is selected using a greedy approach in the first pass, and a “sliding window” approach is used in the second pass to refine the solution. The two-pass method is iteratively performed on a bounded set of candidate hardware accelerators to limit the search space and to avoid local maxima. In order to validate the benefits of the proposed selection algorithm, an exhaustive search algorithm is also developed. Experimental results using the popular CHStone benchmark suite show that the performance achieved by the accelerators recommended by the proposed algorithm closely matches the performance of the exhaustive algorithm, with close to 99% accuracy, while being orders of magnitude faster. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2017.2769125 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 12 StartPage: 445 Subjects: – SubjectFull: Systems on a chip Type: general – SubjectFull: Integrated memory circuits Type: general – SubjectFull: Embedded computer systems Type: general Titles: – TitleFull: Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Prakash, Alok – PersonEntity: Name: NameFull: Clarke, Christopher T. – PersonEntity: Name: NameFull: Lam, Siew-Kei – PersonEntity: Name: NameFull: Srikanthan, Thambipillai IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 26 – Type: issue Value: 3 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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