A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS.

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Title: A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS.
Authors: Wu, Bo1, Zhu, Shuang2, Zhou, Yuan3, Chiu, Yun4
Source: IEEE Journal of Solid-State Circuits. Mar2018, Vol. 53 Issue 3, p839-849. 11p.
Subjects: Time-digital conversion, Digital counters, Time measurements, Quantization (Physics), Quantum theory
Abstract: The first folding-flash time-to-digital converter (TDC) based on the remainder number system (RNS) is reported. In this paper, fine quantization of an input time interval is performed directly with dual free-running ring oscillators without additional circuitry to record the coarse bits. The RNS architecture reduces hardware complexity significantly without speed impairment relative to the full flash counterpart employing delay chains. As a proof-of-concept design, 490 quantization levels using only 84 delay stages achieve a sample rate of 215 MS/s and an LSB size of 9.4 ps. Without trimming or calibration, the measured differential nonlinearity and integral nonlinearity of the RNS TDC prototype are +0.53/−0.57 and +1.1/−1.1 LSBs, respectively. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS.
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  Data: <searchLink fieldCode="AR" term="%22Wu%2C+Bo%22">Wu, Bo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhu%2C+Shuang%22">Zhu, Shuang</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhou%2C+Yuan%22">Zhou, Yuan</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Chiu%2C+Yun%22">Chiu, Yun</searchLink><relatesTo>4</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Mar2018, Vol. 53 Issue 3, p839-849. 11p.
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  Data: <searchLink fieldCode="DE" term="%22Time-digital+conversion%22">Time-digital conversion</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+counters%22">Digital counters</searchLink><br /><searchLink fieldCode="DE" term="%22Time+measurements%22">Time measurements</searchLink><br /><searchLink fieldCode="DE" term="%22Quantization+%28Physics%29%22">Quantization (Physics)</searchLink><br /><searchLink fieldCode="DE" term="%22Quantum+theory%22">Quantum theory</searchLink>
– Name: Abstract
  Label: Abstract
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  Data: The first folding-flash time-to-digital converter (TDC) based on the remainder number system (RNS) is reported. In this paper, fine quantization of an input time interval is performed directly with dual free-running ring oscillators without additional circuitry to record the coarse bits. The RNS architecture reduces hardware complexity significantly without speed impairment relative to the full flash counterpart employing delay chains. As a proof-of-concept design, 490 quantization levels using only 84 delay stages achieve a sample rate of 215 MS/s and an LSB size of 9.4 ps. Without trimming or calibration, the measured differential nonlinearity and integral nonlinearity of the RNS TDC prototype are +0.53/−0.57 and +1.1/−1.1 LSBs, respectively. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/JSSC.2017.2782766
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        Text: English
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      – SubjectFull: Digital counters
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      – SubjectFull: Time measurements
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      – SubjectFull: Quantization (Physics)
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              Text: Mar2018
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