Thermal Aware Test Scheduling for NTV Circuit.
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| Title: | Thermal Aware Test Scheduling for NTV Circuit. |
|---|---|
| Authors: | Lim, Jaeil1, Oh, Hyunggoy1, Kim, Heetae1, Kang, Sungho1 |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Apr2018, Vol. 37 Issue 4, p906-910. 5p. |
| Subjects: | Threshold voltage measurement, Systems on a chip testing, Energy consumption, Electric circuits, Simulation methods & models |
| Abstract: | Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 128555074 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Thermal Aware Test Scheduling for NTV Circuit. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Lim%2C+Jaeil%22">Lim, Jaeil</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Oh%2C+Hyunggoy%22">Oh, Hyunggoy</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kim%2C+Heetae%22">Kim, Heetae</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kang%2C+Sungho%22">Kang, Sungho</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+%26+Systems%22">IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems</searchLink>. Apr2018, Vol. 37 Issue 4, p906-910. 5p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Threshold+voltage+measurement%22">Threshold voltage measurement</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip+testing%22">Systems on a chip testing</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+circuits%22">Electric circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+methods+%26+models%22">Simulation methods & models</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCAD.2017.2729282 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 5 StartPage: 906 Subjects: – SubjectFull: Threshold voltage measurement Type: general – SubjectFull: Systems on a chip testing Type: general – SubjectFull: Energy consumption Type: general – SubjectFull: Electric circuits Type: general – SubjectFull: Simulation methods & models Type: general Titles: – TitleFull: Thermal Aware Test Scheduling for NTV Circuit. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Lim, Jaeil – PersonEntity: Name: NameFull: Oh, Hyunggoy – PersonEntity: Name: NameFull: Kim, Heetae – PersonEntity: Name: NameFull: Kang, Sungho IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 04 Text: Apr2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 02780070 Numbering: – Type: volume Value: 37 – Type: issue Value: 4 Titles: – TitleFull: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems Type: main |
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