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An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.

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Title: An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.
Authors: Ji, Cheng1, Chang, Li-Pin2, Wu, Chao1, Shi, Liang3, Xue, Chun Jason1
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Apr2018, Vol. 37 Issue 4, p756-769. 14p.
Subjects: Computer input-output equipment, Flash memory, Computer scheduling, Random access memory, NAND gates, Embedded computer systems
Abstract: NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.
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  Data: <searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Flash+memory%22">Flash memory</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+scheduling%22">Computer scheduling</searchLink><br /><searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22NAND+gates%22">NAND gates</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink>
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  Data: NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively. [ABSTRACT FROM AUTHOR]
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  Label:
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  Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TCAD.2017.2729405
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      – Code: eng
        Text: English
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        PageCount: 14
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        Type: general
      – SubjectFull: Flash memory
        Type: general
      – SubjectFull: Computer scheduling
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      – SubjectFull: Random access memory
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      – SubjectFull: NAND gates
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      – SubjectFull: Embedded computer systems
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      – TitleFull: An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.
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              Text: Apr2018
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