View in EDS

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging.

Saved in:
Bibliographic Details
Title: Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging.
Authors: Lei Shi1, Lin Chen1, David Wei Zhang1 dwzhang@fudan.edu.cn, Evan Liu2, Qiang Liu2,3, Ching-I Chen4
Source: Journal of Electronic Packaging. Mar2018, Vol. 140 Issue 1, p1-9. 9p.
Subjects: Wafer level packaging, Chip scale packaging, Thermomechanical treatment, Thermal expansion, Printed circuits
Abstract: Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder-post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Electronic Packaging is the property of American Society of Mechanical Engineers and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 128560701
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Lei+Shi%22">Lei Shi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Lin+Chen%22">Lin Chen</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22David+Wei+Zhang%22">David Wei Zhang</searchLink><relatesTo>1</relatesTo><i> dwzhang@fudan.edu.cn</i><br /><searchLink fieldCode="AR" term="%22Evan+Liu%22">Evan Liu</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Qiang+Liu%22">Qiang Liu</searchLink><relatesTo>2,3</relatesTo><br /><searchLink fieldCode="AR" term="%22Ching-I+Chen%22">Ching-I Chen</searchLink><relatesTo>4</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Electronic+Packaging%22">Journal of Electronic Packaging</searchLink>. Mar2018, Vol. 140 Issue 1, p1-9. 9p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Wafer+level+packaging%22">Wafer level packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Thermomechanical+treatment%22">Thermomechanical treatment</searchLink><br /><searchLink fieldCode="DE" term="%22Thermal+expansion%22">Thermal expansion</searchLink><br /><searchLink fieldCode="DE" term="%22Printed+circuits%22">Printed circuits</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder-post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Electronic Packaging is the property of American Society of Mechanical Engineers and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=128560701
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1115/1.4038245
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 9
        StartPage: 1
    Subjects:
      – SubjectFull: Wafer level packaging
        Type: general
      – SubjectFull: Chip scale packaging
        Type: general
      – SubjectFull: Thermomechanical treatment
        Type: general
      – SubjectFull: Thermal expansion
        Type: general
      – SubjectFull: Printed circuits
        Type: general
    Titles:
      – TitleFull: Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Lei Shi
      – PersonEntity:
          Name:
            NameFull: Lin Chen
      – PersonEntity:
          Name:
            NameFull: David Wei Zhang
      – PersonEntity:
          Name:
            NameFull: Evan Liu
      – PersonEntity:
          Name:
            NameFull: Qiang Liu
      – PersonEntity:
          Name:
            NameFull: Ching-I Chen
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 03
              Text: Mar2018
              Type: published
              Y: 2018
          Identifiers:
            – Type: issn-print
              Value: 10437398
          Numbering:
            – Type: volume
              Value: 140
            – Type: issue
              Value: 1
          Titles:
            – TitleFull: Journal of Electronic Packaging
              Type: main
ResultId 1