On Probability of Detection Lossless Concurrent Error Detection Based on Implications.
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| Title: | On Probability of Detection Lossless Concurrent Error Detection Based on Implications. |
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| Authors: | Wang, Chih-Hao1, Hsieh, Tong-Yu1 |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. May2018, Vol. 37 Issue 5, p1090-1103. 14p. |
| Subjects: | Concurrent error detection, Reliability in engineering, Integrated circuits, Fault tolerance (Engineering), Computer programming |
| Abstract: | In recent years, a new concurrent error detection method by using invariant relationships inside a circuit, called implications, has been proposed. Algorithms have also been developed to reduce the total number of required implications so as to minimize the incurred area overhead due to implication checking logic. This implication reduction process, however, would result in degradation on the probability of error detection ( P{\mathrm{ detection}} ) of the method. In this paper, we analyze the impact of this issue mathematically together with illustration by a real case study. Our analytical results show that just one percent degradation on P{\mathrm{ detection}} would result in millions more errors being undetected per second and thereby significant loss on reliability of the target circuit. To address this issue, we develop a new implication reduction algorithm that guarantees no loss on P{\mathrm{ detection}} . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated. The evaluation results are then utilized to select the most efficient candidates for detecting all the detectable errors. We also analyze the computation and memory complexity of the proposed algorithm. The experimental results on 28 representative benchmark circuits from ISCAS’85, ISCAS’89, and ITC’99 show that the implication reduction rate of our method (92.59%) is close to that of the previous work (95.8%). Only a small number of additional implications need to be selected to guarantee no loss on P{\mathrm{ detection}} . [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 129266265 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: On Probability of Detection Lossless Concurrent Error Detection Based on Implications. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Wang%2C+Chih-Hao%22">Wang, Chih-Hao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Hsieh%2C+Tong-Yu%22">Hsieh, Tong-Yu</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+%26+Systems%22">IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems</searchLink>. May2018, Vol. 37 Issue 5, p1090-1103. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Concurrent+error+detection%22">Concurrent error detection</searchLink><br /><searchLink fieldCode="DE" term="%22Reliability+in+engineering%22">Reliability in engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+programming%22">Computer programming</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In recent years, a new concurrent error detection method by using invariant relationships inside a circuit, called implications, has been proposed. Algorithms have also been developed to reduce the total number of required implications so as to minimize the incurred area overhead due to implication checking logic. This implication reduction process, however, would result in degradation on the probability of error detection ( P{\mathrm{ detection}} ) of the method. In this paper, we analyze the impact of this issue mathematically together with illustration by a real case study. Our analytical results show that just one percent degradation on P{\mathrm{ detection}} would result in millions more errors being undetected per second and thereby significant loss on reliability of the target circuit. To address this issue, we develop a new implication reduction algorithm that guarantees no loss on P{\mathrm{ detection}} . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated. The evaluation results are then utilized to select the most efficient candidates for detecting all the detectable errors. We also analyze the computation and memory complexity of the proposed algorithm. The experimental results on 28 representative benchmark circuits from ISCAS’85, ISCAS’89, and ITC’99 show that the implication reduction rate of our method (92.59%) is close to that of the previous work (95.8%). Only a small number of additional implications need to be selected to guarantee no loss on P{\mathrm{ detection}} . [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCAD.2017.2740289 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 1090 Subjects: – SubjectFull: Concurrent error detection Type: general – SubjectFull: Reliability in engineering Type: general – SubjectFull: Integrated circuits Type: general – SubjectFull: Fault tolerance (Engineering) Type: general – SubjectFull: Computer programming Type: general Titles: – TitleFull: On Probability of Detection Lossless Concurrent Error Detection Based on Implications. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Wang, Chih-Hao – PersonEntity: Name: NameFull: Hsieh, Tong-Yu IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: May2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 02780070 Numbering: – Type: volume Value: 37 – Type: issue Value: 5 Titles: – TitleFull: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems Type: main |
| ResultId | 1 |
