Multiple-Core PLC CPU Implementation and Programming.
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| Title: | Multiple-Core PLC CPU Implementation and Programming. |
|---|---|
| Authors: | Milik, Adam1 adam.milik@polsl.pl |
| Source: | Journal of Circuits, Systems & Computers. Sep2018, Vol. 27 Issue 10, pN.PAG-N.PAG. 30p. |
| Subjects: | Computer programming, Field programmable gate arrays, Computer software, Programming languages, Synchronization |
| Abstract: | The paper presents a complete approach to the multithreaded execution of a control program prepared according to IEC61131-3 standard. The program is mapped to a dedicated multiple-core CPU unit. The CPU consists of multiple independent bit and word CPUs. The computation synchronization mechanism is based on memory cells with semaphored access, which enable hardware-level synchronization. The paper presents in detail the architecture, results of implementation and the achieved performance. The custom-developed compiler translates standard programming languages into a multithreaded executable form. It utilizes an original intermediate data flow graph to optimize and recognize program parallelisms. The program is automatically partitioned and mapped to the available computing resources. The paper is concluded with a performance comparison of program executions using the standard single-threaded and proposed approaches. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 129769097 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Multiple-Core PLC CPU Implementation and Programming. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Milik%2C+Adam%22">Milik, Adam</searchLink><relatesTo>1</relatesTo><i> adam.milik@polsl.pl</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>. Sep2018, Vol. 27 Issue 10, pN.PAG-N.PAG. 30p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+programming%22">Computer programming</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software%22">Computer software</searchLink><br /><searchLink fieldCode="DE" term="%22Programming+languages%22">Programming languages</searchLink><br /><searchLink fieldCode="DE" term="%22Synchronization%22">Synchronization</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The paper presents a complete approach to the multithreaded execution of a control program prepared according to IEC61131-3 standard. The program is mapped to a dedicated multiple-core CPU unit. The CPU consists of multiple independent bit and word CPUs. The computation synchronization mechanism is based on memory cells with semaphored access, which enable hardware-level synchronization. The paper presents in detail the architecture, results of implementation and the achieved performance. The custom-developed compiler translates standard programming languages into a multithreaded executable form. It utilizes an original intermediate data flow graph to optimize and recognize program parallelisms. The program is automatically partitioned and mapped to the available computing resources. The paper is concluded with a performance comparison of program executions using the standard single-threaded and proposed approaches. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=129769097 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1142/S0218126618501621 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 30 StartPage: N.PAG Subjects: – SubjectFull: Computer programming Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Computer software Type: general – SubjectFull: Programming languages Type: general – SubjectFull: Synchronization Type: general Titles: – TitleFull: Multiple-Core PLC CPU Implementation and Programming. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Milik, Adam IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 02181266 Numbering: – Type: volume Value: 27 – Type: issue Value: 10 Titles: – TitleFull: Journal of Circuits, Systems & Computers Type: main |
| ResultId | 1 |
