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Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.

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Title: Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.
Authors: Telagam, Nagarjuna1 nagarjuna473@gmail.com, Kandasamy, Nehru1 nnehruk@gmail.com
Source: Majlesi Journal of Electrical Engineering. Mar2018, Vol. 12 Issue 1, p103-108. 6p.
Subjects: Computer arithmetic & logic units, Semiconductors, Energy dissipation, Digital electronics, Decoders (Electronics), Central processing units
Abstract: The semiconductor circuits dissipate energy in the form of binary digits. This dissipation of energy is in the form of power consumption. ALU is complex circuit and is one of many components within CPU. It performs mathematical and bitwise operations. This paper proposes a new low power 8 bit ALU digital circuit for nano scale regions. The proposed ALU has two 4x1 data selectors, 2x4 decoder and an adder circuit as sub modules. The output of 2x4 decoder is connected to 3 input NAND, AND, OR, XOR gates. The low power adder and multiplexer are proposed and it is used for ALU design. With the help of selection lines of multiplexer, the conventional operations of ALU such as logical operations are performed. This proposed ALU caters the need of digital signal processing tools. Present ALU structure is simulated in Linux Computer using Cadence Virtuoso software and implemented in 180nm technology. The proposed ALU has delay of 386.0ps and average power of 677.2uW. The power delay product shows 65.58 % improvement when compared to the conventional 8-bit ALU design. [ABSTRACT FROM AUTHOR]
Copyright of Majlesi Journal of Electrical Engineering is the property of OICC Press and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.
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  Data: <searchLink fieldCode="AR" term="%22Telagam%2C+Nagarjuna%22">Telagam, Nagarjuna</searchLink><relatesTo>1</relatesTo><i> nagarjuna473@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Kandasamy%2C+Nehru%22">Kandasamy, Nehru</searchLink><relatesTo>1</relatesTo><i> nnehruk@gmail.com</i>
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  Data: <searchLink fieldCode="JN" term="%22Majlesi+Journal+of+Electrical+Engineering%22">Majlesi Journal of Electrical Engineering</searchLink>. Mar2018, Vol. 12 Issue 1, p103-108. 6p.
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  Data: <searchLink fieldCode="DE" term="%22Computer+arithmetic+%26+logic+units%22">Computer arithmetic & logic units</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductors%22">Semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+dissipation%22">Energy dissipation</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Decoders+%28Electronics%29%22">Decoders (Electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Central+processing+units%22">Central processing units</searchLink>
– Name: Abstract
  Label: Abstract
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  Data: The semiconductor circuits dissipate energy in the form of binary digits. This dissipation of energy is in the form of power consumption. ALU is complex circuit and is one of many components within CPU. It performs mathematical and bitwise operations. This paper proposes a new low power 8 bit ALU digital circuit for nano scale regions. The proposed ALU has two 4x1 data selectors, 2x4 decoder and an adder circuit as sub modules. The output of 2x4 decoder is connected to 3 input NAND, AND, OR, XOR gates. The low power adder and multiplexer are proposed and it is used for ALU design. With the help of selection lines of multiplexer, the conventional operations of ALU such as logical operations are performed. This proposed ALU caters the need of digital signal processing tools. Present ALU structure is simulated in Linux Computer using Cadence Virtuoso software and implemented in 180nm technology. The proposed ALU has delay of 386.0ps and average power of 677.2uW. The power delay product shows 65.58 % improvement when compared to the conventional 8-bit ALU design. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Majlesi Journal of Electrical Engineering is the property of OICC Press and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Text: English
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        PageCount: 6
        StartPage: 103
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      – SubjectFull: Computer arithmetic & logic units
        Type: general
      – SubjectFull: Semiconductors
        Type: general
      – SubjectFull: Energy dissipation
        Type: general
      – SubjectFull: Digital electronics
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      – SubjectFull: Decoders (Electronics)
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      – SubjectFull: Central processing units
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      – TitleFull: Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.
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              Text: Mar2018
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              Y: 2018
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