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Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree.

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Title: Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree.
Authors: Chen, Li1, Chen, Mo1, Wang, Haibin1, Liu, Rui1, Chen, Qingyu1, Li, Yuanqing1,2, Krstic, Milos2,3, Nofal, Issam4, Shi, Shuting5, Guo, Gang5, Baeg, Sang H.6, Wen, Shi-Jie7, Wong, Richard7
Source: Microelectronics Reliability. Aug2018, Vol. 87, p24-32. 9p.
Subjects: Soft errors, Clock distribution networks, Electric inverters, Integrated circuits, Simulation methods & models
Abstract: The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method. [ABSTRACT FROM AUTHOR]
ISSN:00262714
DOI:10.1016/j.microrel.2018.05.016