Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines.
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| Title: | Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines. |
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| Authors: | Raji, Mohsen1,2 mraji@shirazu.ac.ir, Ghavami, Behnam3 ghavamib@uk.ac.ir |
| Source: | Journal of Supercomputing. Aug2018, Vol. 74 Issue 8, p3820-3840. 21p. |
| Subjects: | Asynchronous circuits, Digital electronics, Nanotechnology, Constraints (Physics), Electronic circuits |
| Abstract: | The class of quasi-delay-insensitive (QDI) asynchronous circuits provides a promising approach toward tolerating process variations. However, the fundamental assumption of QDI circuits is that some wires in such circuits are isochronic; this assumption is more and more challenged by the shrinking technology. This paper redresses the weakest fork timing constraints for QDI asynchronous pipelines to work correctly under arbitrary wire and gate delay variability. We model a QDI circuit using the signal transition graph and propose a method to detect isochronic fork candidates. Extensive analysis is exploited to justify the necessary and sufficient isochronic fork selections of a QDI template. The proposed method works for many QDI templates, and it provides some necessary information about the constraint on any wire fork required for an asynchronous EDA tool in nanotechnology era. Experimental results demonstrate that the proposed method results in more robust QDI circuits in the expense of the least design overheads comparing to the similar method suggested in the current literature. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 131260160 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Raji%2C+Mohsen%22">Raji, Mohsen</searchLink><relatesTo>1,2</relatesTo><i> mraji@shirazu.ac.ir</i><br /><searchLink fieldCode="AR" term="%22Ghavami%2C+Behnam%22">Ghavami, Behnam</searchLink><relatesTo>3</relatesTo><i> ghavamib@uk.ac.ir</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Aug2018, Vol. 74 Issue 8, p3820-3840. 21p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Asynchronous+circuits%22">Asynchronous circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Nanotechnology%22">Nanotechnology</searchLink><br /><searchLink fieldCode="DE" term="%22Constraints+%28Physics%29%22">Constraints (Physics)</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuits%22">Electronic circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The class of quasi-delay-insensitive (QDI) asynchronous circuits provides a promising approach toward tolerating process variations. However, the fundamental assumption of QDI circuits is that some wires in such circuits are isochronic; this assumption is more and more challenged by the shrinking technology. This paper redresses the weakest fork timing constraints for QDI asynchronous pipelines to work correctly under arbitrary wire and gate delay variability. We model a QDI circuit using the signal transition graph and propose a method to detect isochronic fork candidates. Extensive analysis is exploited to justify the necessary and sufficient isochronic fork selections of a QDI template. The proposed method works for many QDI templates, and it provides some necessary information about the constraint on any wire fork required for an asynchronous EDA tool in nanotechnology era. Experimental results demonstrate that the proposed method results in more robust QDI circuits in the expense of the least design overheads comparing to the similar method suggested in the current literature. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11227-017-2056-0 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 21 StartPage: 3820 Subjects: – SubjectFull: Asynchronous circuits Type: general – SubjectFull: Digital electronics Type: general – SubjectFull: Nanotechnology Type: general – SubjectFull: Constraints (Physics) Type: general – SubjectFull: Electronic circuits Type: general Titles: – TitleFull: Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Raji, Mohsen – PersonEntity: Name: NameFull: Ghavami, Behnam IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 09208542 Numbering: – Type: volume Value: 74 – Type: issue Value: 8 Titles: – TitleFull: Journal of Supercomputing Type: main |
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