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Optimizing inter-nest data locality in imperfect stencils based on loop blocking.

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Title: Optimizing inter-nest data locality in imperfect stencils based on loop blocking.
Authors: Seyfari, Yousef1, Lotfi, Shahriar1, Karimpour, Jaber1
Source: Journal of Supercomputing. Oct2018, Vol. 74 Issue 10, p5432-5460. 29p.
Subjects: Loop tiling (Computer science), Evolutionary algorithms, High performance computing, Computer memory management, Central processing units, Graphics processing units
Abstract: With the interesting growth in high-performance computing, the performance of data-driven programs is becoming more and more dependent on fast memory access, which can be improved by data locality. Data locality between a pair of loop nest is called inter-nest data locality. A very important class of loop nests that shows a significant inter-nest data locality is stencils. In this paper, we have proposed a method to optimize inter-nest data locality in stencils and named it EALB. In the proposed method, two “compute” and “copy” loop nests within the time loop nest of stencils are partitioned into blocks and these blocks are executed interleaved. Determining the optimum block size in the proposed method is based on an evolutionary algorithm which uses cache miss rate and cache eviction rate. The experimental results show that the EALB is significantly effective compared to the original programs and has better results compared to the results of the state-of-the-art approach, Pluto. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: With the interesting growth in high-performance computing, the performance of data-driven programs is becoming more and more dependent on fast memory access, which can be improved by data locality. Data locality between a pair of loop nest is called inter-nest data locality. A very important class of loop nests that shows a significant inter-nest data locality is stencils. In this paper, we have proposed a method to optimize inter-nest data locality in stencils and named it EALB. In the proposed method, two “compute” and “copy” loop nests within the time loop nest of stencils are partitioned into blocks and these blocks are executed interleaved. Determining the optimum block size in the proposed method is based on an evolutionary algorithm which uses cache miss rate and cache eviction rate. The experimental results show that the EALB is significantly effective compared to the original programs and has better results compared to the results of the state-of-the-art approach, Pluto. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1007/s11227-018-2443-1
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        Text: English
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      – SubjectFull: Loop tiling (Computer science)
        Type: general
      – SubjectFull: Evolutionary algorithms
        Type: general
      – SubjectFull: High performance computing
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      – SubjectFull: Computer memory management
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      – SubjectFull: Central processing units
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      – SubjectFull: Graphics processing units
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      – TitleFull: Optimizing inter-nest data locality in imperfect stencils based on loop blocking.
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            – D: 01
              M: 10
              Text: Oct2018
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