View in EDS

Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology.

Saved in:
Bibliographic Details
Title: Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology.
Authors: Limachia, Mitesh Jethabhai1,2,3 miteshjlimachia@rediffmail.com, Thakker, Rajesh A.1,2,3 rathakker2008@gmail.com, Kothari, Nikhil J.1,2,3 njkothari@gmail.com
Source: Circuit World. 2018, Vol. 44 Issue 4, p187-194. 8p.
Subjects: Integrated memory circuits, Transistors, Writing, Data, Static relays
Abstract: Purpose This paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.Design/methodology/approach A new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.Findings The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.Originality/value The proposed bit-cell is novel compared with existing bit-cells. [ABSTRACT FROM AUTHOR]
Copyright of Circuit World is the property of Emerald Publishing Limited and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 132459197
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Limachia%2C+Mitesh+Jethabhai%22">Limachia, Mitesh Jethabhai</searchLink><relatesTo>1,2,3</relatesTo><i> miteshjlimachia@rediffmail.com</i><br /><searchLink fieldCode="AR" term="%22Thakker%2C+Rajesh+A%2E%22">Thakker, Rajesh A.</searchLink><relatesTo>1,2,3</relatesTo><i> rathakker2008@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Kothari%2C+Nikhil+J%2E%22">Kothari, Nikhil J.</searchLink><relatesTo>1,2,3</relatesTo><i> njkothari@gmail.com</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Circuit+World%22">Circuit World</searchLink>. 2018, Vol. 44 Issue 4, p187-194. 8p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Transistors%22">Transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Writing%22">Writing</searchLink><br /><searchLink fieldCode="DE" term="%22Data%22">Data</searchLink><br /><searchLink fieldCode="DE" term="%22Static+relays%22">Static relays</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Purpose This paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.Design/methodology/approach A new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.Findings The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.Originality/value The proposed bit-cell is novel compared with existing bit-cells. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Circuit World is the property of Emerald Publishing Limited and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=132459197
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1108/CW-01-2018-0002
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 8
        StartPage: 187
    Subjects:
      – SubjectFull: Integrated memory circuits
        Type: general
      – SubjectFull: Transistors
        Type: general
      – SubjectFull: Writing
        Type: general
      – SubjectFull: Data
        Type: general
      – SubjectFull: Static relays
        Type: general
    Titles:
      – TitleFull: Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Limachia, Mitesh Jethabhai
      – PersonEntity:
          Name:
            NameFull: Thakker, Rajesh A.
      – PersonEntity:
          Name:
            NameFull: Kothari, Nikhil J.
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 10
              Text: 2018
              Type: published
              Y: 2018
          Identifiers:
            – Type: issn-print
              Value: 03056120
          Numbering:
            – Type: volume
              Value: 44
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: Circuit World
              Type: main
ResultId 1