View in EDS

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.

Saved in:
Bibliographic Details
Title: X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
Authors: Agrawal, Amogh, Jaiswal, Akhilesh, Lee, Chankyu, Roy, Kaushik
Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Dec2018, Vol. 65 Issue 12, p4219-4232. 14p.
Subjects: Boolean algebra, CMOS memory circuits, Random access memory, Metal oxide semiconductor field-effect transistor testing, Artificial intelligence
Abstract: Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, to a large extent, result from the well-known von-Neumann bottleneck. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications such as artificial intelligence, machine learning, and cryptography. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable in-memory Boolean computations. In this paper, we present an augmented version of the conventional SRAM bit-cells, called the X-SRAM, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations, including NAND, NOR, IMP (implication), XOR logic gates, with respect to different bit-cell topologies − the 8T cell and the 8+T Differential cell. In addition, we also present a novel ‘read-compute-store’ scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the proposed techniques. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 132683357
AccessLevel: 6
PubType: Periodical
PubTypeId: serialPeriodical
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Agrawal%2C+Amogh%22">Agrawal, Amogh</searchLink><br /><searchLink fieldCode="AR" term="%22Jaiswal%2C+Akhilesh%22">Jaiswal, Akhilesh</searchLink><br /><searchLink fieldCode="AR" term="%22Lee%2C+Chankyu%22">Lee, Chankyu</searchLink><br /><searchLink fieldCode="AR" term="%22Roy%2C+Kaushik%22">Roy, Kaushik</searchLink>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+I%3A+Regular+Papers%22">IEEE Transactions on Circuits & Systems. Part I: Regular Papers</searchLink>. Dec2018, Vol. 65 Issue 12, p4219-4232. 14p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Boolean+algebra%22">Boolean algebra</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Metal+oxide+semiconductor+field-effect+transistor+testing%22">Metal oxide semiconductor field-effect transistor testing</searchLink><br /><searchLink fieldCode="DE" term="%22Artificial+intelligence%22">Artificial intelligence</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, to a large extent, result from the well-known von-Neumann bottleneck. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications such as artificial intelligence, machine learning, and cryptography. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable in-memory Boolean computations. In this paper, we present an augmented version of the conventional SRAM bit-cells, called the X-SRAM, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations, including NAND, NOR, IMP (implication), XOR logic gates, with respect to different bit-cell topologies − the 8T cell and the 8+T Differential cell. In addition, we also present a novel ‘read-compute-store’ scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the proposed techniques. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=132683357
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/TCSI.2018.2848999
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 14
        StartPage: 4219
    Subjects:
      – SubjectFull: Boolean algebra
        Type: general
      – SubjectFull: CMOS memory circuits
        Type: general
      – SubjectFull: Random access memory
        Type: general
      – SubjectFull: Metal oxide semiconductor field-effect transistor testing
        Type: general
      – SubjectFull: Artificial intelligence
        Type: general
    Titles:
      – TitleFull: X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Agrawal, Amogh
      – PersonEntity:
          Name:
            NameFull: Jaiswal, Akhilesh
      – PersonEntity:
          Name:
            NameFull: Lee, Chankyu
      – PersonEntity:
          Name:
            NameFull: Roy, Kaushik
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 12
              Text: Dec2018
              Type: published
              Y: 2018
          Identifiers:
            – Type: issn-print
              Value: 15498328
          Numbering:
            – Type: volume
              Value: 65
            – Type: issue
              Value: 12
          Titles:
            – TitleFull: IEEE Transactions on Circuits & Systems. Part I: Regular Papers
              Type: main
ResultId 1