HCDN: Hybrid-Mode Clock Distribution Networks.
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| Title: | HCDN: Hybrid-Mode Clock Distribution Networks. |
|---|---|
| Authors: | Islam, Riadul, Guthaus, Matthew R. |
| Source: | IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Jan2019, Vol. 66 Issue 1, p251-262. 12p. |
| Subjects: | Hybrid power systems, Clock distribution networks, Signal processing |
| Abstract: | We propose a new hybrid clock distribution scheme that uses global current-mode and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1–2-GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1- and 2-GHz clock frequency, respectively. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 133501399 AccessLevel: 6 PubType: Periodical PubTypeId: serialPeriodical PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: HCDN: Hybrid-Mode Clock Distribution Networks. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Islam%2C+Riadul%22">Islam, Riadul</searchLink><br /><searchLink fieldCode="AR" term="%22Guthaus%2C+Matthew+R%2E%22">Guthaus, Matthew R.</searchLink> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+I%3A+Regular+Papers%22">IEEE Transactions on Circuits & Systems. Part I: Regular Papers</searchLink>. Jan2019, Vol. 66 Issue 1, p251-262. 12p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Hybrid+power+systems%22">Hybrid power systems</searchLink><br /><searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+processing%22">Signal processing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: We propose a new hybrid clock distribution scheme that uses global current-mode and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1–2-GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1- and 2-GHz clock frequency, respectively. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCSI.2018.2866224 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 12 StartPage: 251 Subjects: – SubjectFull: Hybrid power systems Type: general – SubjectFull: Clock distribution networks Type: general – SubjectFull: Signal processing Type: general Titles: – TitleFull: HCDN: Hybrid-Mode Clock Distribution Networks. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Islam, Riadul – PersonEntity: Name: NameFull: Guthaus, Matthew R. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2019 Type: published Y: 2019 Identifiers: – Type: issn-print Value: 15498328 Numbering: – Type: volume Value: 66 – Type: issue Value: 1 Titles: – TitleFull: IEEE Transactions on Circuits & Systems. Part I: Regular Papers Type: main |
| ResultId | 1 |
