High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication.
Saved in:
| Title: | High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication. |
|---|---|
| Authors: | Ding, Jinnan, Li, Shuguo, Gu, Zhen |
| Source: | IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Mar2019, Vol. 66 Issue 3, p1003-1016. 14p. |
| Subjects: | Analog multipliers, Multiplying circuits |
| Abstract: | In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom–Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 $\mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $\mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 134602213 AccessLevel: 6 PubType: Periodical PubTypeId: serialPeriodical PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ding%2C+Jinnan%22">Ding, Jinnan</searchLink><br /><searchLink fieldCode="AR" term="%22Li%2C+Shuguo%22">Li, Shuguo</searchLink><br /><searchLink fieldCode="AR" term="%22Gu%2C+Zhen%22">Gu, Zhen</searchLink> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+I%3A+Regular+Papers%22">IEEE Transactions on Circuits & Systems. Part I: Regular Papers</searchLink>. Mar2019, Vol. 66 Issue 3, p1003-1016. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Analog+multipliers%22">Analog multipliers</searchLink><br /><searchLink fieldCode="DE" term="%22Multiplying+circuits%22">Multiplying circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom–Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 $\mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $\mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=134602213 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCSI.2018.2878598 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 1003 Subjects: – SubjectFull: Analog multipliers Type: general – SubjectFull: Multiplying circuits Type: general Titles: – TitleFull: High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ding, Jinnan – PersonEntity: Name: NameFull: Li, Shuguo – PersonEntity: Name: NameFull: Gu, Zhen IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2019 Type: published Y: 2019 Identifiers: – Type: issn-print Value: 15498328 Numbering: – Type: volume Value: 66 – Type: issue Value: 3 Titles: – TitleFull: IEEE Transactions on Circuits & Systems. Part I: Regular Papers Type: main |
| ResultId | 1 |
