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Highly Linear Low-Power Wireless RF Receiver for WSN.

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Title: Highly Linear Low-Power Wireless RF Receiver for WSN.
Authors: Elsayed, Omar1 (AUTHOR) omarelsayed@tamu.edu, Zarate-Roldan, Jorge1 (AUTHOR), Abuellil, Amr1 (AUTHOR), Hussien, Faisal Abdel-Latif2 (AUTHOR), Eladawy, Ahmed2 (AUTHOR), Sanchez-Sinencio, Edgar1 (AUTHOR)
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. May2019, Vol. 27 Issue 5, p1007-1016. 10p.
Subjects: Wireless sensor networks, Current-mode circuits
Abstract: This paper introduces a low-power wireless RF receiver for the wireless sensor network. The receiver has improved linearity with incorporated current-mode circuits and high-selectivity filtering. The receiver operates at the 900-MHz industrial, scientific, and medical band and is implemented in 130-nm CMOS technology. The receiver has a frequency multiplication mixer, which uses a 300-MHz clock from a local oscillator (LO). The LO is implemented using vertical delay cells to reduce power consumption. The receiver conversion gain is 40 dB and the receiver noise figure is 14 dB. The receiver’s input third-order intercept point (IIP3) is −6 dBm and the total power consumption is 1.16 mW. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 136117395
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  Data: This paper introduces a low-power wireless RF receiver for the wireless sensor network. The receiver has improved linearity with incorporated current-mode circuits and high-selectivity filtering. The receiver operates at the 900-MHz industrial, scientific, and medical band and is implemented in 130-nm CMOS technology. The receiver has a frequency multiplication mixer, which uses a 300-MHz clock from a local oscillator (LO). The LO is implemented using vertical delay cells to reduce power consumption. The receiver conversion gain is 40 dB and the receiver noise figure is 14 dB. The receiver’s input third-order intercept point (IIP3) is −6 dBm and the total power consumption is 1.16 mW. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TVLSI.2018.2890093
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        Text: English
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              Text: May2019
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