Scalable Construction of Clock Trees With Useful Skew and High Timing Quality.
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| Title: | Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. |
|---|---|
| Authors: | Ewetz, Rickard1, Koh, Cheng-Kok2 |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jun2019, Vol. 38 Issue 6, p1161-1174. 14p. |
| Subjects: | Clock distribution networks, Algorithms, Foundations of arithmetic, Eigenfactor, Clock & watch industry |
| Abstract: | Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, there is a tradeoff between timing margin utilization and run-time. In this paper, a scalable clock tree synthesis (CTS) framework is proposed for the construction of low-cost useful skew trees (USTs) with high timing quality. The scalability is based on combining the use of arrival time constraints with virtual minimum and maximum delay offsets, which facilitates that a pair of smaller subtrees can be joined into a larger subtree in constant time. The ability to quickly join subtrees is leveraged to perform a high degree of solution space exploration, which translates into the construction of USTs with low-cost. In particular, clock trees with various routing tree topologies, buffer tree topologies, buffer sizes, and stem wire lengths are explored. Moreover, the arrival time constraints are specified with the objective of being the least restrictive to reduce cost. Furthermore, the constraints are respecified throughout the tree construction process using a slack graph (SG) to expose additional timing margins. The high timing quality is obtained by seamlessly integrating arbitrary timing models using the SG. Finally, the proposed CTS framework is integrated with a clock tree optimization framework to demonstrate that the constructed USTs are capable of meeting timing constraints under the influence of on-chip variations. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 136543544 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ewetz%2C+Rickard%22">Ewetz, Rickard</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Koh%2C+Cheng-Kok%22">Koh, Cheng-Kok</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+%26+Systems%22">IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems</searchLink>. Jun2019, Vol. 38 Issue 6, p1161-1174. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Foundations+of+arithmetic%22">Foundations of arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22Eigenfactor%22">Eigenfactor</searchLink><br /><searchLink fieldCode="DE" term="%22Clock+%26+watch+industry%22">Clock & watch industry</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, there is a tradeoff between timing margin utilization and run-time. In this paper, a scalable clock tree synthesis (CTS) framework is proposed for the construction of low-cost useful skew trees (USTs) with high timing quality. The scalability is based on combining the use of arrival time constraints with virtual minimum and maximum delay offsets, which facilitates that a pair of smaller subtrees can be joined into a larger subtree in constant time. The ability to quickly join subtrees is leveraged to perform a high degree of solution space exploration, which translates into the construction of USTs with low-cost. In particular, clock trees with various routing tree topologies, buffer tree topologies, buffer sizes, and stem wire lengths are explored. Moreover, the arrival time constraints are specified with the objective of being the least restrictive to reduce cost. Furthermore, the constraints are respecified throughout the tree construction process using a slack graph (SG) to expose additional timing margins. The high timing quality is obtained by seamlessly integrating arbitrary timing models using the SG. Finally, the proposed CTS framework is integrated with a clock tree optimization framework to demonstrate that the constructed USTs are capable of meeting timing constraints under the influence of on-chip variations. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCAD.2018.2834437 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 1161 Subjects: – SubjectFull: Clock distribution networks Type: general – SubjectFull: Algorithms Type: general – SubjectFull: Foundations of arithmetic Type: general – SubjectFull: Eigenfactor Type: general – SubjectFull: Clock & watch industry Type: general Titles: – TitleFull: Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ewetz, Rickard – PersonEntity: Name: NameFull: Koh, Cheng-Kok IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2019 Type: published Y: 2019 Identifiers: – Type: issn-print Value: 02780070 Numbering: – Type: volume Value: 38 – Type: issue Value: 6 Titles: – TitleFull: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems Type: main |
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