Downscaling of Floating-Gate EEPROM Modules for ASIC Applications.
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| Title: | Downscaling of Floating-Gate EEPROM Modules for ASIC Applications. |
|---|---|
| Authors: | Shiba, Kazuyoshi1, Kubota, Katsuhiko1 |
| Source: | Electronics & Communications in Japan, Part 2: Electronics. Dec92, Vol. 75 Issue 12, p67-76. 10p. |
| Subjects: | Integrated circuits, Read-only memory, Electronic circuits, Scaling laws (Statistical physics), Logic circuits, Computer circuits |
| Abstract: | Downscaling methods of electrically erasable pros grammable ROM (EEPROM) for application-specific integrated circuit (ASIC) applications based on the double-poly floating-gate process were studied. Simple sealing of ASIC and EEPROM modules with the same scaling factor can significantly reduce the time for design and development. Horizontal scaling of the memory cell with unchanged vertical dimensions does not alter the cell performance because the capacitance coupling ratios are kept constant. Vertical scaling, which further reduces the cell size due to less short channel effects, requires the improvement in the tunnel oxide quality. For this purpose, an improved process also was studied in terms of process temperature and phosphorus concentration in polysilicon gate. [ABSTRACT FROM AUTHOR] |
| Copyright of Electronics & Communications in Japan, Part 2: Electronics is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 14078357 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Downscaling of Floating-Gate EEPROM Modules for ASIC Applications. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Shiba%2C+Kazuyoshi%22">Shiba, Kazuyoshi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kubota%2C+Katsuhiko%22">Kubota, Katsuhiko</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Electronics+%26+Communications+in+Japan%2C+Part+2%3A+Electronics%22">Electronics & Communications in Japan, Part 2: Electronics</searchLink>. Dec92, Vol. 75 Issue 12, p67-76. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Read-only+memory%22">Read-only memory</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuits%22">Electronic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Scaling+laws+%28Statistical+physics%29%22">Scaling laws (Statistical physics)</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+circuits%22">Computer circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Downscaling methods of electrically erasable pros grammable ROM (EEPROM) for application-specific integrated circuit (ASIC) applications based on the double-poly floating-gate process were studied. Simple sealing of ASIC and EEPROM modules with the same scaling factor can significantly reduce the time for design and development. Horizontal scaling of the memory cell with unchanged vertical dimensions does not alter the cell performance because the capacitance coupling ratios are kept constant. Vertical scaling, which further reduces the cell size due to less short channel effects, requires the improvement in the tunnel oxide quality. For this purpose, an improved process also was studied in terms of process temperature and phosphorus concentration in polysilicon gate. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Electronics & Communications in Japan, Part 2: Electronics is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1002/ecjb.4420751208 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 67 Subjects: – SubjectFull: Integrated circuits Type: general – SubjectFull: Read-only memory Type: general – SubjectFull: Electronic circuits Type: general – SubjectFull: Scaling laws (Statistical physics) Type: general – SubjectFull: Logic circuits Type: general – SubjectFull: Computer circuits Type: general Titles: – TitleFull: Downscaling of Floating-Gate EEPROM Modules for ASIC Applications. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Shiba, Kazuyoshi – PersonEntity: Name: NameFull: Kubota, Katsuhiko IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec92 Type: published Y: 1992 Identifiers: – Type: issn-print Value: 8756663X Numbering: – Type: volume Value: 75 – Type: issue Value: 12 Titles: – TitleFull: Electronics & Communications in Japan, Part 2: Electronics Type: main |
| ResultId | 1 |
