Reconfigurable parallelized TCAM architecture based on enhanced static memory cell.
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| Title: | Reconfigurable parallelized TCAM architecture based on enhanced static memory cell. |
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| Authors: | Sakthi, K1 (AUTHOR) sakthisav12345@gmail.com, Kumar, Dr. P. Nirmal2 (AUTHOR) nirmal@annauniv.edu |
| Source: | Microprocessors & Microsystems. Jul2020, Vol. 76, pN.PAG-N.PAG. 1p. |
| Subjects: | Field programmable gate arrays, Random access memory, Parallel programming, Gate array circuits |
| Abstract: | Associative memories with tristate-based web crawlers assume a vital job in systems administration switches. The hunt space requests of ternary associative memories applications are always rising. In any case, existing acknowledge where content addressable memories can enter door clusters gate arrays experience the ill effects of capacity wastefulness. The proposed idea introduces high speed search engines empowered and intertwined with many internal ports of static memory cell put together ternary associative memories structure comparing with FPGA, to accomplish an effective usage of static arrangement of memories. Previous versions of static memory cell's exploits answers for this renewable solution and also diminish maximizing expansion provided in this customary Ternary content addressable memory design specifications leading with rapid and enormous development of static memories on behalf of unique utilizing fell square Static memories called block random access memories (BRAMs) over the boards of FPGA. Nonetheless, best in class FPGAs which entitled as block RAM have a base profundity restriction, which confines the capacity productivity for ternary associative memories bits. Our proposed arrangement maintains a strategic distance from this restriction with a provision of uniting and linking the customary idea of ternary memories and its table split-ups as an alternative of partitioned squares which is so called arranged block RAMs, along these lines accomplishing associative and productive ternary CAM memory structure. The arrangement works as arrangement of basic double block memories which was planned as static memories of many input and output ports which utilizing higher parallelism, influencing speeder and vital inner clock recurrence for getting partial-squares leading to block random memories in unique individual framework cycle. Actualized this novel structure on a Virtuoso environment of version six field programmable gate array gadget. Contrasted and in the earlier versions of gate array ternary content memories plans, this strategy accomplishes speeding of two and half of its occasions faster execution of its memory unit cycle. [ABSTRACT FROM AUTHOR] |
| Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 143553180 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Reconfigurable parallelized TCAM architecture based on enhanced static memory cell. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Sakthi%2C+K%22">Sakthi, K</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> sakthisav12345@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Kumar%2C+Dr%2E+P%2E+Nirmal%22">Kumar, Dr. P. Nirmal</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> nirmal@annauniv.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Jul2020, Vol. 76, pN.PAG-N.PAG. 1p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+programming%22">Parallel programming</searchLink><br /><searchLink fieldCode="DE" term="%22Gate+array+circuits%22">Gate array circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Associative memories with tristate-based web crawlers assume a vital job in systems administration switches. The hunt space requests of ternary associative memories applications are always rising. In any case, existing acknowledge where content addressable memories can enter door clusters gate arrays experience the ill effects of capacity wastefulness. The proposed idea introduces high speed search engines empowered and intertwined with many internal ports of static memory cell put together ternary associative memories structure comparing with FPGA, to accomplish an effective usage of static arrangement of memories. Previous versions of static memory cell's exploits answers for this renewable solution and also diminish maximizing expansion provided in this customary Ternary content addressable memory design specifications leading with rapid and enormous development of static memories on behalf of unique utilizing fell square Static memories called block random access memories (BRAMs) over the boards of FPGA. Nonetheless, best in class FPGAs which entitled as block RAM have a base profundity restriction, which confines the capacity productivity for ternary associative memories bits. Our proposed arrangement maintains a strategic distance from this restriction with a provision of uniting and linking the customary idea of ternary memories and its table split-ups as an alternative of partitioned squares which is so called arranged block RAMs, along these lines accomplishing associative and productive ternary CAM memory structure. The arrangement works as arrangement of basic double block memories which was planned as static memories of many input and output ports which utilizing higher parallelism, influencing speeder and vital inner clock recurrence for getting partial-squares leading to block random memories in unique individual framework cycle. Actualized this novel structure on a Virtuoso environment of version six field programmable gate array gadget. Contrasted and in the earlier versions of gate array ternary content memories plans, this strategy accomplishes speeding of two and half of its occasions faster execution of its memory unit cycle. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.micpro.2020.103073 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 1 StartPage: N.PAG Subjects: – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Random access memory Type: general – SubjectFull: Parallel programming Type: general – SubjectFull: Gate array circuits Type: general Titles: – TitleFull: Reconfigurable parallelized TCAM architecture based on enhanced static memory cell. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Sakthi, K – PersonEntity: Name: NameFull: Kumar, Dr. P. Nirmal IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2020 Type: published Y: 2020 Identifiers: – Type: issn-print Value: 01419331 Numbering: – Type: volume Value: 76 Titles: – TitleFull: Microprocessors & Microsystems Type: main |
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