Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions.
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| Title: | Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions. |
|---|---|
| Authors: | Kujofsa, T.1 tedi.kujofsa@gmail.com, Ayers, J. E.1 |
| Source: | Journal of Electronic Materials. Nov2020, Vol. 49 Issue 11, p6977-6982. 6p. |
| Subjects: | Gettering, Semiconductors, Auditing standards |
| Abstract: | It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnSySe1-y/GaAs (001) relative to ZnSe/GaAs (001). [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Electronic Materials is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 146433526 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kujofsa%2C+T%2E%22">Kujofsa, T.</searchLink><relatesTo>1</relatesTo><i> tedi.kujofsa@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Ayers%2C+J%2E+E%2E%22">Ayers, J. E.</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Electronic+Materials%22">Journal of Electronic Materials</searchLink>. Nov2020, Vol. 49 Issue 11, p6977-6982. 6p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Gettering%22">Gettering</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductors%22">Semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Auditing+standards%22">Auditing standards</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnSySe1-y/GaAs (001) relative to ZnSe/GaAs (001). [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Electronic Materials is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11664-020-08353-x Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 6 StartPage: 6977 Subjects: – SubjectFull: Gettering Type: general – SubjectFull: Semiconductors Type: general – SubjectFull: Auditing standards Type: general Titles: – TitleFull: Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kujofsa, T. – PersonEntity: Name: NameFull: Ayers, J. E. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2020 Type: published Y: 2020 Identifiers: – Type: issn-print Value: 03615235 Numbering: – Type: volume Value: 49 – Type: issue Value: 11 Titles: – TitleFull: Journal of Electronic Materials Type: main |
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