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Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator.

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Title: Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator.
Authors: Ning Chen1 ningchen3461@163.com, Man Zhang1 manzhang1128@163.com
Source: Journal of Vibroengineering. Dec2020, Vol. 22 Issue 8, p1847-1858. 12p.
Subjects: Preamplifiers, Comparator circuits, Successive approximation analog-to-digital converters, Analog-to-digital converters
Abstract: Analog and digital converters (ADCs) are the most inevitable part of today's high-speed human interacted devices. Continuous efforts are being made to improve their performance. Despite working for the improvement of whole ADC, efforts to improve sub-modules are also significant. Comparators are also a vital part of ADC. In this work, we have proposed a novel high-speed Balanced-Input Balanced-Output (BIBO) preamplifier latch based comparator design, to be used for the designing of an Asynchronous Successive Approximation Resister (SAR) ADC. In order to make comparison faster, we have employed Preamplifier-Latch based comparator. Transistor fingering is used to save area and makes large transistor easy to handle without changing their aspect ratio. We have implemented this latch using two back to back connected inverters. These inverters are farming a positive feedback arrangement that also prohibits the comparator from bursting into the oscillation. Latch circuit uses three non-overlapping phases namely phi1, phi2 and phi3 and dissipates less power when operated on a single 1V supply voltage. All these features collectively made this comparator expedient and obtained results confirm that it can be used effectively for the designing of SAR ADC. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Vibroengineering is the property of Extrica and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator.
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  Data: <searchLink fieldCode="AR" term="%22Ning+Chen%22">Ning Chen</searchLink><relatesTo>1</relatesTo><i> ningchen3461@163.com</i><br /><searchLink fieldCode="AR" term="%22Man+Zhang%22">Man Zhang</searchLink><relatesTo>1</relatesTo><i> manzhang1128@163.com</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Vibroengineering%22">Journal of Vibroengineering</searchLink>. Dec2020, Vol. 22 Issue 8, p1847-1858. 12p.
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  Data: <searchLink fieldCode="DE" term="%22Preamplifiers%22">Preamplifiers</searchLink><br /><searchLink fieldCode="DE" term="%22Comparator+circuits%22">Comparator circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Successive+approximation+analog-to-digital+converters%22">Successive approximation analog-to-digital converters</searchLink><br /><searchLink fieldCode="DE" term="%22Analog-to-digital+converters%22">Analog-to-digital converters</searchLink>
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  Data: Analog and digital converters (ADCs) are the most inevitable part of today's high-speed human interacted devices. Continuous efforts are being made to improve their performance. Despite working for the improvement of whole ADC, efforts to improve sub-modules are also significant. Comparators are also a vital part of ADC. In this work, we have proposed a novel high-speed Balanced-Input Balanced-Output (BIBO) preamplifier latch based comparator design, to be used for the designing of an Asynchronous Successive Approximation Resister (SAR) ADC. In order to make comparison faster, we have employed Preamplifier-Latch based comparator. Transistor fingering is used to save area and makes large transistor easy to handle without changing their aspect ratio. We have implemented this latch using two back to back connected inverters. These inverters are farming a positive feedback arrangement that also prohibits the comparator from bursting into the oscillation. Latch circuit uses three non-overlapping phases namely phi1, phi2 and phi3 and dissipates less power when operated on a single 1V supply voltage. All these features collectively made this comparator expedient and obtained results confirm that it can be used effectively for the designing of SAR ADC. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Vibroengineering is the property of Extrica and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.21595/jve.2020.21485
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      – Code: eng
        Text: English
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        PageCount: 12
        StartPage: 1847
    Subjects:
      – SubjectFull: Preamplifiers
        Type: general
      – SubjectFull: Comparator circuits
        Type: general
      – SubjectFull: Successive approximation analog-to-digital converters
        Type: general
      – SubjectFull: Analog-to-digital converters
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      – TitleFull: Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator.
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            NameFull: Ning Chen
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            NameFull: Man Zhang
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              M: 12
              Text: Dec2020
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              Y: 2020
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