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On‐chip communication for neuro‐glia networks.

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Title: On‐chip communication for neuro‐glia networks.
Authors: Martin, George1 (AUTHOR) martin‐g11@ulster.ac.uk, Harkin, Jim1 (AUTHOR), McDaid, Liam J.1 (AUTHOR), Wade, John J.1 (AUTHOR), Liu, Junxiu1 (AUTHOR)
Source: IET Computers & Digital Techniques (Wiley-Blackwell). Jul2018, Vol. 12 Issue 4, p130-138. 9p.
Abstract: Hardware has become more prone to faults as a result of geometric scaling, wear‐out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self‐repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self‐repair within models of neural networks known as neuro‐glia networks. This astrocyte‐driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro‐glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine‐grained self‐repair process. Therefore, mapping neuro‐glia networks to hardware provides a strategy for achieving self‐repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self‐repair process is dependent on the communication infrastructure between astrocyte‐to‐astrocyte; e.g. astrocyte network. This study addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements. [ABSTRACT FROM AUTHOR]
Copyright of IET Computers & Digital Techniques (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 148454873
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– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Hardware has become more prone to faults as a result of geometric scaling, wear‐out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self‐repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self‐repair within models of neural networks known as neuro‐glia networks. This astrocyte‐driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro‐glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine‐grained self‐repair process. Therefore, mapping neuro‐glia networks to hardware provides a strategy for achieving self‐repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self‐repair process is dependent on the communication infrastructure between astrocyte‐to‐astrocyte; e.g. astrocyte network. This study addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IET Computers & Digital Techniques (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1049/iet-cdt.2017.0187
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        Text: English
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              Text: Jul2018
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