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A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.

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Title: A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.
Authors: Wu, Lianbo1 (AUTHOR) lwu@iis.ee.ethz.ch, Burger, Thomas1 (AUTHOR), Schonle, Philipp1 (AUTHOR), Huang, Qiuting1 (AUTHOR)
Source: IEEE Journal of Solid-State Circuits. Apr2021, Vol. 56 Issue 4, p1254-1264. 11p.
Subjects: Successive approximation analog-to-digital converters, Digital-to-analog converters, Analog-to-digital converters, Time-digital conversion, Phase-locked loops, Frequency synthesizers, Quantization (Physics)
Abstract: This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential dv/dt ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of −250.3 dB. The measured worst case fractional spur level is −56 dBc. [ABSTRACT FROM AUTHOR]
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Description
Abstract:This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential dv/dt ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of −250.3 dB. The measured worst case fractional spur level is −56 dBc. [ABSTRACT FROM AUTHOR]
ISSN:00189200
DOI:10.1109/JSSC.2020.3047431