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A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.

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Title: A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.
Authors: Wu, Lianbo1 (AUTHOR) lwu@iis.ee.ethz.ch, Burger, Thomas1 (AUTHOR), Schonle, Philipp1 (AUTHOR), Huang, Qiuting1 (AUTHOR)
Source: IEEE Journal of Solid-State Circuits. Apr2021, Vol. 56 Issue 4, p1254-1264. 11p.
Subjects: Successive approximation analog-to-digital converters, Digital-to-analog converters, Analog-to-digital converters, Time-digital conversion, Phase-locked loops, Frequency synthesizers, Quantization (Physics)
Abstract: This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential dv/dt ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of −250.3 dB. The measured worst case fractional spur level is −56 dBc. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Apr2021, Vol. 56 Issue 4, p1254-1264. 11p.
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  Label: Abstract
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  Data: This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential dv/dt ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of −250.3 dB. The measured worst case fractional spur level is −56 dBc. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/JSSC.2020.3047431
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      – Code: eng
        Text: English
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        PageCount: 11
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      – SubjectFull: Successive approximation analog-to-digital converters
        Type: general
      – SubjectFull: Digital-to-analog converters
        Type: general
      – SubjectFull: Analog-to-digital converters
        Type: general
      – SubjectFull: Time-digital conversion
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      – SubjectFull: Phase-locked loops
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      – SubjectFull: Frequency synthesizers
        Type: general
      – SubjectFull: Quantization (Physics)
        Type: general
    Titles:
      – TitleFull: A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.
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            NameFull: Wu, Lianbo
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            NameFull: Burger, Thomas
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            NameFull: Schonle, Philipp
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            NameFull: Huang, Qiuting
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              M: 04
              Text: Apr2021
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              Y: 2021
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            – TitleFull: IEEE Journal of Solid-State Circuits
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