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Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET.

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Title: Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET.
Authors: Sharma, Suruchi1 sharma.suru91@gmail.com, Basu, Rikmantra1, Kaur, Baljit1
Source: IET Circuits, Devices & Systems (Wiley-Blackwell). Aug2021, Vol. 15 Issue 5, p424-433. 10p.
Subjects: Heterojunction field effect transistors, Germanium, Electric potential, Semiconductors, Voltage
Abstract: The interface trap charges (ITC) associated reliability analysis of a charge‐plasma based asymmetric double‐gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high‐κ gate dielectric (HJADGDLTFET) has been studied. The HJADGDLTFET uses silicon at the drain and the channel region, and germanium at the source region, which enhances the band‐to‐band tunnelling at the source‐channel junction, and hence drive current is increased by one order concerning ADGDLTFET. Also, ADG and high‐κ dielectric (HfO2) have been used to maintain low off‐state current values. The primary intention of this work is to investigate the impact of ITC for HJADGDLTFET and compare it for ADGDLTFET considering DC, analog/RF, and linearity parameters such as transfer characteristics, electric‐field, electric potential, first‐, second‐, and third‐order transconductances (gm1, gm2, and gm3), gate‐to‐drain capacitance (Cgd), cut‐off frequency (fT), gain–bandwidth product, device efficiency, second‐ and third‐order voltage intercept points (VIP2, VIP3), third‐order input intercept points (IIP3), and third‐order intermodulation distortion. The ATLAS simulation results show that the HJADGDLTFET is more immune to ITC variation than conventional ADGDLTFET concerning different polarities of ITC available at the semiconductor‐oxide interface. [ABSTRACT FROM AUTHOR]
Copyright of IET Circuits, Devices & Systems (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 151433909
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  Label: Title
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  Data: Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET.
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  Data: <searchLink fieldCode="AR" term="%22Sharma%2C+Suruchi%22">Sharma, Suruchi</searchLink><relatesTo>1</relatesTo><i> sharma.suru91@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Basu%2C+Rikmantra%22">Basu, Rikmantra</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kaur%2C+Baljit%22">Kaur, Baljit</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IET+Circuits%2C+Devices+%26+Systems+%28Wiley-Blackwell%29%22">IET Circuits, Devices & Systems (Wiley-Blackwell)</searchLink>. Aug2021, Vol. 15 Issue 5, p424-433. 10p.
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  Data: <searchLink fieldCode="DE" term="%22Heterojunction+field+effect+transistors%22">Heterojunction field effect transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Germanium%22">Germanium</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+potential%22">Electric potential</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductors%22">Semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Voltage%22">Voltage</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: The interface trap charges (ITC) associated reliability analysis of a charge‐plasma based asymmetric double‐gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high‐κ gate dielectric (HJADGDLTFET) has been studied. The HJADGDLTFET uses silicon at the drain and the channel region, and germanium at the source region, which enhances the band‐to‐band tunnelling at the source‐channel junction, and hence drive current is increased by one order concerning ADGDLTFET. Also, ADG and high‐κ dielectric (HfO2) have been used to maintain low off‐state current values. The primary intention of this work is to investigate the impact of ITC for HJADGDLTFET and compare it for ADGDLTFET considering DC, analog/RF, and linearity parameters such as transfer characteristics, electric‐field, electric potential, first‐, second‐, and third‐order transconductances (gm1, gm2, and gm3), gate‐to‐drain capacitance (Cgd), cut‐off frequency (fT), gain–bandwidth product, device efficiency, second‐ and third‐order voltage intercept points (VIP2, VIP3), third‐order input intercept points (IIP3), and third‐order intermodulation distortion. The ATLAS simulation results show that the HJADGDLTFET is more immune to ITC variation than conventional ADGDLTFET concerning different polarities of ITC available at the semiconductor‐oxide interface. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IET Circuits, Devices & Systems (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1049/cds2.12037
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      – Code: eng
        Text: English
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        PageCount: 10
        StartPage: 424
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      – SubjectFull: Heterojunction field effect transistors
        Type: general
      – SubjectFull: Germanium
        Type: general
      – SubjectFull: Electric potential
        Type: general
      – SubjectFull: Semiconductors
        Type: general
      – SubjectFull: Voltage
        Type: general
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      – TitleFull: Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET.
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            NameFull: Sharma, Suruchi
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            NameFull: Basu, Rikmantra
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            – D: 01
              M: 08
              Text: Aug2021
              Type: published
              Y: 2021
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