APA (7th ed.) Citation

Siddiqui, M. S. M., Lee, Z. C., & Kim, T. T. (2021). A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(10), 1707. https://doi.org/10.1109/TVLSI.2021.3102675

Chicago Style (17th ed.) Citation

Siddiqui, M. Sultan M., Zhao Chuan Lee, and Tony Tae-Hyoung Kim. "A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, no. 10 (2021): 1707. https://doi.org/10.1109/TVLSI.2021.3102675.

MLA (9th ed.) Citation

Siddiqui, M. Sultan M., et al. "A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 10, 2021, p. 1707, https://doi.org/10.1109/TVLSI.2021.3102675.