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Logic-level mapping of high-level faults

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Title: Logic-level mapping of high-level faults
Authors: Fummi, F.1 franco.fummi@univr.it, Marconcini, C. marconcini@sci.univr.it, Pravadelli, G.1 pravadelli@sci.univr.it
Source: Integration: The VLSI Journal. Jan2005, Vol. 38 Issue 3, p467-490. 24p.
Subjects: Fault-tolerant computing, Electronic data processing, Computer system failures, Algorithms
Abstract: Abstract: Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model? The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology. [Copyright &y& Elsevier]
Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 15561130
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: <searchLink fieldCode="AR" term="%22Fummi%2C+F%2E%22">Fummi, F.</searchLink><relatesTo>1</relatesTo><i> franco.fummi@univr.it</i><br /><searchLink fieldCode="AR" term="%22Marconcini%2C+C%2E%22">Marconcini, C.</searchLink><i> marconcini@sci.univr.it</i><br /><searchLink fieldCode="AR" term="%22Pravadelli%2C+G%2E%22">Pravadelli, G.</searchLink><relatesTo>1</relatesTo><i> pravadelli@sci.univr.it</i>
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  Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Jan2005, Vol. 38 Issue 3, p467-490. 24p.
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  Data: Abstract: Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model? The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology. [Copyright &y& Elsevier]
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  Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – SubjectFull: Electronic data processing
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              Text: Jan2005
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