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Power efficient network selector placement in control plane of multiple networks-on-chip.

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Title: Power efficient network selector placement in control plane of multiple networks-on-chip.
Authors: Yadav, Sonal1,2 (AUTHOR) syadav.cse@nitrr.ac.in, Raj, Ritu3 (AUTHOR)
Source: Journal of Supercomputing. Apr2022, Vol. 78 Issue 5, p6664-6695. 32p.
Subjects: Network interface devices, Software-defined networking, Delay lines, Communication infrastructure, Network routers, Parallel processing, Electric circuit networks
Abstract: Multiple networks-on-chip is a popular on-chip interconnect. This parallel communication infrastructure uses more than one NoCs to facilitate customized traffic distribution. Parallel architectures improve performance, however, at the cost of huge power dissipation. We propose power efficient customized placement of network selector hardware unit in the control plane at router. A network selector hardware unit is essentially used to distribute traffic between NoCs. Conventionally, this unit is placed in the data plane at network interface. We place network selector at switch allocator and at the routing unit of the router. The placement at switch allocator is more efficient than placement at routing unit or network interface. It improves 21% static power, 29% dynamic power, and 33% critical path delay of the circuit over network interface placement. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Power efficient network selector placement in control plane of multiple networks-on-chip.
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  Data: <searchLink fieldCode="AR" term="%22Yadav%2C+Sonal%22">Yadav, Sonal</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> syadav.cse@nitrr.ac.in</i><br /><searchLink fieldCode="AR" term="%22Raj%2C+Ritu%22">Raj, Ritu</searchLink><relatesTo>3</relatesTo> (AUTHOR)
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Apr2022, Vol. 78 Issue 5, p6664-6695. 32p.
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  Data: <searchLink fieldCode="DE" term="%22Network+interface+devices%22">Network interface devices</searchLink><br /><searchLink fieldCode="DE" term="%22Software-defined+networking%22">Software-defined networking</searchLink><br /><searchLink fieldCode="DE" term="%22Delay+lines%22">Delay lines</searchLink><br /><searchLink fieldCode="DE" term="%22Communication+infrastructure%22">Communication infrastructure</searchLink><br /><searchLink fieldCode="DE" term="%22Network+routers%22">Network routers</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+processing%22">Parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+circuit+networks%22">Electric circuit networks</searchLink>
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  Data: Multiple networks-on-chip is a popular on-chip interconnect. This parallel communication infrastructure uses more than one NoCs to facilitate customized traffic distribution. Parallel architectures improve performance, however, at the cost of huge power dissipation. We propose power efficient customized placement of network selector hardware unit in the control plane at router. A network selector hardware unit is essentially used to distribute traffic between NoCs. Conventionally, this unit is placed in the data plane at network interface. We place network selector at switch allocator and at the routing unit of the router. The placement at switch allocator is more efficient than placement at routing unit or network interface. It improves 21% static power, 29% dynamic power, and 33% critical path delay of the circuit over network interface placement. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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    Identifiers:
      – Type: doi
        Value: 10.1007/s11227-021-04098-4
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 32
        StartPage: 6664
    Subjects:
      – SubjectFull: Network interface devices
        Type: general
      – SubjectFull: Software-defined networking
        Type: general
      – SubjectFull: Delay lines
        Type: general
      – SubjectFull: Communication infrastructure
        Type: general
      – SubjectFull: Network routers
        Type: general
      – SubjectFull: Parallel processing
        Type: general
      – SubjectFull: Electric circuit networks
        Type: general
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      – TitleFull: Power efficient network selector placement in control plane of multiple networks-on-chip.
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            – D: 01
              M: 04
              Text: Apr2022
              Type: published
              Y: 2022
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              Value: 78
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            – TitleFull: Journal of Supercomputing
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